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ST6365,ST6375,ST6385 ST6367,ST6377,ST6387
8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING
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4.5 to 6V supply operating range 8MHz Maximum Clock Frequency User Program ROM: up to 20140 bytes Reserved Test ROM: up to 340 bytes Data ROM: user selectable size Data RAM: 256 bytes Data EEPROM: 384 bytes 42-Pin Shrink Dual in Line Plastic Package Up to 22 software programmable general purpose Inputs/Outputs, including 2 direct LED driving Outputs Two Timers each including an 8-bit counter with a 7-bit programmable prescaler Digital Watchdog Function Serial Peripheral Interface (SPI) supporting SBUS/ I 2 C BUS and standard serial protocols SPI for external frequency synthesis tuning 14 bit counter for voltage synthesis tuning Up to Six 6-Bit PWM D/A Converters AFC A/D converter with 0.5V resolution Five interrupt vectors (IRIN/NMI, Timer 1 & 2, VSYNC, PWR INT.) On-chip clock oscillator 5 Lines by 15 Characters On-Screen Display Generator with 128 Characters All ROM types are supported by pin-to-pin EPROM and OTP versions. The development tool of the ST6365, ST6375, ST6385, ST6367, ST6377, ST6387 microcontrollers consists of the ST638X-EMU2 emulation and development system to be connected via a standard RS232 serial line to an MS-DOS Personal Computer.
PSDIP42
(Refer to end of Document for Ordering Information)
DEVICE SUMMARY
DEVICE ST6365 ST6367 ST6375 ST6377 ST6385 ST6387 ROM (Bytes) 8K 8K 14K 14K 20K 20K D/A Converter 4 6 4 6 4 6
Rev. 2.2
December 1997
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
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Table of Contents
ST6365, ST6375, ST6385, ST6367, ST6377, ST6387 . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.1 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.4 Data RAM/EEPROM/OSD RAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 18 3.1 ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.1 RESET Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 MCU Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . . . 3.4.1 Interrupt Vectors/Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Interrupt Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 ST638x Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Exit from WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Details of I/O Ports . . . . . . . . . . . 4.1.2 I/O Pin Programming . . . . . . . . . 4.1.3 Input/Output Configurations . . . . 4.1.4 I/O Port Registers . . . . . . . . . . . 4.2 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 4.2.2 4.2.3 4.2.4 ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... 19 19 20 20 20 21 23 23 24 24 25 26 26 26 26 27 27 28 30 30 30 31 32 33 33 33
3.4 INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Status Control Registers (TSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Counter Registers (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Prescaler Registers (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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4.3 SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.1 S-BUS/I2C BUS Protocol Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 S-BUS/I2C BUS Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Compatibility S-BUS/I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 STD SPI Protocol (Shift Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 SPI Data/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 14-BIT VOLTAGE SYNTHESIS TUNING PERIPHERAL . . . . . . . . . . . . . . . . . . . . . . . . . . 34 37 39 40 40 43
4.4.1 Output Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4.2 VS Tuning Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.5 6-BIT PWM D/A CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.6 AFC A/D COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.6.1 A/D Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.7 DEDICATED LATCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.8 ON-SCREEN DISPLAY (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.8.1 Format Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3 CUSTOMER EEPROM INITIAL CONTENTS: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.4 OSD TEST CHARACTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.5 ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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ST63E85, T85, ST63E87, T87 . . . . . . . . . . . . . . . . . . . . . . . . . . 71
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.3 EPROM/OTP DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.4 POWER ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.5 EPROM ERASING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 2.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.2 CUSTOMER EEPROM INITIAL CONTENTS: FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.3 OSD TEST CHARACTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.4 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.5 ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST6365,67,75,77,85,87 microcontrollers are members of the 8-bit HCMOS ST638x family, a series of devices specially oriented to TV applications. Different ROM size and peripheral configurations are available to give the maximum application and cost flexibility. All ST638x members are based on a building block approach: a common core is surrounded by a combination of on-chip peripherals (macrocells) available from a standard library. These peripherals are designed with the same Core technology providing full compatibility and short design time. Many of these macrocells are specially dedicated to TV applications. The macrocells of the ST638x family are: two Timer peripherals each including an 8-bit counter with a Table 1. Device Summary
Device ST6365 ST6367 ST6375 ST6377 ST6385 ST6387 ROM (Bytes) 8K 8K 14K 14K 20K 20K RAM (Bytes) 256 256 256 256 256 256 EEPROM (Bytes) 384 384 384 384 384 384 AFC Yes Yes Yes Yes Yes Yes VS Yes Yes Yes Yes Yes Yes D/A 4 6 4 6 4 6 Colour Pins 3 3 3 3 3 3 EPROM Devices ST63E85 ST63E87 ST63E85 ST63E87 ST63E85 ST63E87
7-bit software programmable prescaler (Timer), a digital hardware activated watchdog function (DHWD), a 14-bit voltage synthesis tuning peripheral, a Serial Peripheral Interface (SPI), up to six 6-bit PWM D/A converters, an AFC A/D converter with 0.5V resolution, an on-screen display (OSD) with 15 characters per line and 128 characters (in two banks each of 64 characters). In addition the following memory resources are available: program ROM (up to 20K), data RAM (256 bytes), EEPROM (384 bytes). Refer to pin configurations figures and to ST638x device summary (Table 1) for the definition of ST638x family members and a summary of differences among the different types.
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Figure 1. Block Diagram
PORT A TEST TEST PORT B IRIN/PC6 INTERRUPT Inputs DATA ROM USER SELECTABLE DATA RAM 256 Bytes DATA EEPROM 384 Bytes PORT C
PA0 - PA7* PB0 - PB2, PB4 PB6*
USER PROGRAM MEMORY UP TO 20KBytes
Serial Peripheral Interface
PC2, PC4 - PC7* PC0/SCL PC1/SDA PC3/SEN
TIMER 1
TIMER 2
PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER SUPPLY OSCILLATOR RESET 8 BIT CORE
Digital Watchdog Timer D/A Outputs VS Output & AFC Outputs On-Screen Display DA0 - DA5
AFC & VS* R, G, B, BLANK HSYNC, VSYNC
VDD VSS
OSCin OSCout
RESET
OSDOSCout
OSDOSCin VR01753
*Refer to Pin Description for Additional Information
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1.2 PIN DESCRIPTION VDD and VSS. Power is supplied to the MCU using these two pins. VDD is power and VSS is the ground connection. OSCin, OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the correct operation of the MCU with various stability/ cost trade-offs. The OSCin pin is the input pin, the OSCout pin is the output pin. RESET. The active low RESET pin is used to start the microcontroller to the beginning of its program. Additionally the quartz crystal oscillator will be disabled when the RESET pin is low to reduce power consumption during reset phase. TEST. The TEST pin must be held at VSS for normal operation. PA0-PA7. These 8 lines are organized as one I/O port (A). Each line may be configured as either an input with or without pull-up resistor or as an output under software control of the data direction register. Pins PA4 to PA7 are configured as opendrain outputs (12V drive). On PA4-PA7 pins the input pull-up option is not available while PA6 and PA7 have additional current driving capability (25mA, VOL:1V). PA0 to PA3 pins are configured as push-pull. PB0-PB2, PB4-PB6. These 6 lines are organized as one I/O port (B). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register. PC0-PC7. These 8 lines are organized as one I/O port (C). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register. Pins PC0 to PC3 are configured as open-drain (5V drive) in output mode while PC4 to PC7 are open-drain with 12V drive and the input pull-up options does not exist on these four pins. PC0, PC1 and PC3 lines when in output mode are "ANDed" with the SPI control signals and are all open-drain. PC0 is connected to the SPI clock signal (SCL), PC1 with the SPI data signal (SDA) while PC3 is connected with SPI enable signal (SEN, used in S-BUS protocol). Pin PC4 and PC6 can also be inputs to software programmable edge sensitive latches which can generate interrupts; PC4 can be connected to Power Interrupt while PC6 can be connected to the IRIN/NMI interrupt line. DA0-DA5. These pins are the six PWM D/A outputs of the 6-bit on-chip D/A converters. These lines have open-drain outputs with 12V drive. The output repetition rate is 31.25KHz (with 8MHz clock). AFC. This is the input of the on-chip 10 levels comparator that can be used to implement the AFC function. This pin is an high impedance input able to withstand signals with a peak amplitude up to 12V. OSDOSCin, OSDOSCout. These are the On Screen Display oscillator terminals. An oscillation capacitor and coil network have to be connected to provide the right signal to the OSD. HSYNC, VSYNC. These are the horizontal and vertical synchronization pins. The active polarity of these pins to the OSD macrocell can be selected by the user as ROM mask option. If the device is specified to have negative logic inputs, then these signals are low the OSD oscillator stops. If the device is specified to have positive logic inputs, then when these signals are high the OSD oscillator stops. VSYNC is also connected to the VSYNC interrupt. R, G, B, BLANK. Outputs from the OSD. R, G and B are the color outputs while BLANK is the blanking output. All outputs are push-pull. The active polarity of these pins can be selected by the user as ROM mask option. VS. This is the output pin of the on-chip 14-bit voltage synthesis tuning cell (VS). The tuning signal present at this pin gives an approximate resolution of 40KHz per step over the UHF band. This line is a push-pull output with standard drive.
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Figure 2. ST6365, 75, 85 Pin configuration
VS DA1 DA2 DA3 DA4 PB0 PB1 PB2 AFC PB4 PB5 PB6 PA0 PA1 PA2 PA3 PA4 PA5 PA6 (HD0) PA7 (HD1) VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD PC0/SCL PC1/SDA PC2 PC3/SEN PC4/PWRIN PC5 PC6/IRIN PC7 RESET OSCout OSCin TEST/VPP (1) OSDOSCin OSDOSCout VSYNC HSYNC BLANK B G R
VR01375
Figure 3. ST6367, 77, 87 Pin configuration
DA0 DA1 DA2 DA3 DA4 DA5 PB1 PB2 AFC PB4 PB5 PB6 PA0 PA1 PA2 PA3 PA4 PA5 PA6 (HD0) PA7 (HD1) VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD PC0/SCL PC1/SDA PC2 PC3/SEN PC4/PWRIN PC5 PC6/IRIN VS RESET OSCout OSCin TEST/VPP (1) OSDOSCin OSDOSCout VSYNC HSYNC BLANK B G R
VR01375E
(1) This pin is also the VPP input for OTP/EPROM devices
(1) This pin is also the VPP input for OTP/EPROM devices
Table 2. Pin Summary
Pin Function DA0 to DA5 AFC VS R, G, B, BLANK HSYNC, VSYNC OSDOSCin OSDOSCout TEST OSCin OSCout RESET PA0- PA3 PA4- PA5 PA6- PA7 PB0- PB2 PB4- PB6 PC0- PC3 PC4- PC7 VDD, VSS Description Output, Open- Drain, 12V Input, High Impedance, 12V Output, Push- Pull Output, Push- Pull Input, Pull- up, Schmitt Trigger Input, High Impedance Output, Push- Pull Input, Pull- Down Input, Resistive Bias, Schmitt Trigger to Reset Logic Only Output, Push- Pull Input, Pull- up, Schmitt Trigger Input I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input, High Drive I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input I/ O, Open- Drain, 5V, Software Input Pull- up, Schmitt Trigger Input I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input Power Supply Pins
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1.3 MEMORY SPACES The MCU operates in three different memory spaces: Stack Space, Program Space and Data Space. 1.3.1 Stack Space The stack space consists of six 12 bit registers that are used for stacking subroutine and interrupt return addresses plus the current program counter register. 1.3.2 Program Space The program space is physically implemented in the ROM and includes all the instructions that are to be executed, as well as the data required for the immediate addressing mode instructions, the reserved test area and the user vectors. It is addressed thanks to the 12-bit Program Counter register (PC register) and the ST6 Core can directly address up to 4K bytes of Program Space. Nevertheless, the Program Space can be extended by the addition of 2Kbyte memory banks as it is shown in Figure 4, in which the 20K bytes memory is described. These banks are addressed by pointing to the 000h-7FFh locations of the Program Space thanks to the Program Counter, and by writing the appropriate code in the Program ROM Page Register (PRPR) located at address CAh in the Data Space. Because interrupts and common subroutines should be available all the time only the lower 2K byte of the 4K program space are bank switched while the upper 2K byte can be Figure 5. Memory Addressing Diagram
STACK SPACE PROGRAM SPACE DATA SPACE
seen as static space. Table 3 gives the different codes that allows the selection of the corresponding banks. Note that, from the memory point of view, the Page 1 and the Static Page represent the same physical memory: it is only a different way of addressing the same location. On the ST6385 and ST6387, a total of 20480 bytes of ROM have been implemented; 20140 bytes are available as User ROM while 340 bytes are reserved for testing. Figure 4. 20K-Byte Program Space Addressing
Program counter space 0000h 0FFFh Page 1 Static Page 0800h 07FFh Page 0 Page 1 Static Page 0000h
4FFFh
...
Page 9
0000h PROGRAM COUNTER ROM STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 ROM 07FFh 0800h 0-63
000h RAM / EEPROM BANKING AREA 03Fh 040h DATA ROM WINDOW 07Fh 080h 081h 082h 083h 084h 0C0h X Y V W REGISTER REGISTER REGISTER REGISTER RAM DATA ROM WINDOW SELECT DATA RAM BANK SELECT 0FFh ACCUMULATOR
0FF0h INTERRUPT & RESET VECTORS 0FFFh
vr01568
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MEMORY SPACES (Cont'd) Program ROM Page Register (PRPR) Address: CAh - Write only Reset Value: XXh
7 0 PRPR3 PRPR2 PRPR1 PRPR0
D7-D4. These bits are not used but have to be written to "0". PRPR3-PRPR0. These are the program ROM banking bits and the value loaded selects the corresponding page to be addressed in the lower part of 4K program address space as specified in Table 3. This register is undefined on reset. Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. Note. Only the lower part of address space has been bankswitched because interrupt vectors and common subroutines should be available all the time. The reason of this structure is due to the fact that it is not possible to jump from a dynamic page to another, unless jumping back to the static page, changing contents of PRPR and then jumping to a different dynamic page. Care is required when handling the PRPR as it is write only. For this reason, it is not allowed to change the PRPR contents while executing interrupts drivers, as the driver cannot save and than Table 4. Program Memory Map
Program Memory Page PAGE 0
restore its previous content. Anyway, this operation may be necessary if the sum of common routines and interrupt drivers will take more than 2K bytes; in this case it could be necessary to divide the interrupt driver in a (minor) part in the static page (start and end), and in the second (major) part in one dynamic page. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location. Each time the program writes the PRPR register, the image register should also be written. The image register must be written first, so if an interrupt occurs between the two instructions the PRPR is not affected. Table 3. Program Memory Page Register coding
PRPR3 PRPR2 PRPR1 PRPR0 PC11 Memory Page Static Page X X X X 1 (Page 1) 0 0 0 0 0 Page 0 Page 1 (Static 0 0 0 1 0 Page) 0 0 1 0 0 Page 2 0 0 1 1 0 Page 3 0 1 0 0 0 Page 4 0 1 0 1 0 Page 5 0 1 1 0 0 Page 6 0 1 1 1 0 Page 7 1 0 0 0 0 Page 8 1 0 0 1 0 Page 9
PAGE 1 "STATIC"
PAGE 2 PAGE 3 PAGE 4 PAGE 5 PAGE 6 PAGE 7 PAGE 8 PAGE 9
Device Address 0000h-007Fh 0080h-07FFh 0800h-0F9Fh 0FA0h-0FEFh 0FF0h-0FF7h 0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh 0000h-000Fh 0010h-07FFh
Description Reserved User ROM User ROM Reserved Interrupt Vectors Reserved NMI Vector Reset Vector Reserved User ROM Reserved User ROM (End of 8K ST6365, 67) Reserved User ROM Reserved User ROM Reserved User ROM (End of 14K ST6375, 77) Reserved User ROM Reserved User ROM Reserved User ROM (End of 20K ST6385, 87)
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MEMORY SPACES (Cont'd) 1.3.3 Data Space The ST6 Core instruction set operates on a specific space, referred to as the Data Space, which contains all the data necessary for the program.
The Data Space allows the addressing of RAM (256 bytes), EEPROM (384 bytes), ST6 Core and peripheral registers, as well as read-only data such as constants and look-up tables.
Figure 6. Data Space
DATA RAM/EEPROM/OSD BANK AREA DATA ROM WINDOW AREA X REGISTER Y REGISTER V REGISTER W REGISTER DATA RAM PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER RESERVED PORT A DIRECTION REGISTER PORT B DIRECTION REGISTER PORT C DIRECTION REGISTER RESERVED INTERRUPT OPTION REGISTER DATA ROM WINDOW REGISTER PROGRAM ROM PAGE REGISTER RESERVED SPI DATA REGISTER RESERVED TIMER 1 PRESCALER REGISTER TIMER 1 COUNTER REGISTER TIMER 1 STATUS/CONTROL REGISTER RESERVED WATCHDOG REGISTER 000h 03Fh 040h 07Fh 080h 081h 082h 083h 084h 0BFh 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h 0C9h 0CAh 0CBh 0CCh 0CDh 0D1h 0D2h 0D3h 0D4h 0D5h 0D7h 0D8h
RESERVED TIMER 2 PRESCALER REGISTER TIMER 2 COUNTER REGISTER TIMER 2 STATUS/CONTROL REGISTER RESERVED DA 0 DATA/CONTROL REGISTER DA 1 DATA/CONTROL REGISTER DA 2 DATA/CONTROL REGISTER DA 3 DATA/CONTROL REGISTER AFC, IR & OSD RESULT REGISTER OUTPUT CONTROL REGISTER 1 DA 4 DATA/CONTROL REGISTER DA 5 DATA/CONTROL REGISTER DEDICATED LATCHES CONTROL REGISTER EEPROM CONTROL REGISTER SPI CONTROL REGISTER 1 SPI CONTROL REGISTER 2 OSD CHARACTER BANK SELECT REGISTER VS DATA REGISTER 1 VS DATA REGISTER 2
0D9h 0DAh 0DBh 0DCh 0DDh 0DFh 0E0h 0E1h 0E2h 0E3h 0E5h 0E6h 0E7h 0E8h 0E9h 0EAh 0EBh 0ECh 0EDh 0EEh 0EFh 0F0h 0F5h 0FEh 0FFh
RESERVED ACCUMULATOR OSD CONTROL REGISTERS LOCATED IN PAGE 6 OF BANKED DATA RAM VERTICAL START ADDRESS REGISTER HORIZONTAL START ADDRESS REGISTER VERTICAL SPACE REGISTER HORIZONTAL SPACE REGISTER BACKGROUND COLOUR REGISTER GLOBAL ENABLE REGISTER
010h 011h 012h 013h 014h 017h
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MEMORY SPACES (Cont'd) Data ROM Addressing. All the read-only data are physically implemented in the ROM in which the Program Space is also implemented. The ROM therefore contains the program to be executed and also the constants and the look-up tables needed for the program. The locations of Data Space in which the different constants and look-up tables are addressed by the ST6 Core can be considered as being a 64-byte window through which it is possible to access to the read-only data stored in the ROM. This window is located from the 40h address to the 7Fh address in the Data space and allows the direct reading of the bytes from the 000h address to the 03Fh address in the ROM. All the bytes of the ROM can be used to store either instructions or read-only data. Indeed, the window can be moved by step of 64 bytes along the ROM in writing the appropriate code in the Write-only Data ROM Window register (DRWR, location C9h). The effective address of the byte to be read as a data in the ROM is obtained by the concatenation of the 6 less significant bits of the address in the Data Space (as less significant bits) and the content of the DRWR (as most significant bits). So when addressing location 40h of data space, and 0 is loaded in the DRWR, the physical addressed location in ROM is 00h. Note: The data ROM Window can not address window above the 16K byte range. Figure 7. Data ROM Window Memory Addressing
13 12 6 11 5 10 4 9 3 8 2 7 1 6 0
Data ROM Window Register (DRWR) Address: C9h - Write only Reset Value: XXh
7 0 DRWR DRWR DRWR DRWR DRWR DRWR DRWR DRWR 7 6 5 4 3 2 1 0
DRWR7-DRWR0. These are the Data Rom Window bits that correspond to the upper bits of data ROM program space. This register is undefined after reset. Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. Note: Care is required when handling the DRWR as it is write only. For this reason, it is not allowed to change the DRWR contents while executing interrupts drivers, as the driver cannot save and than restore its previous content. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the DRWR it writes also the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRWR register is not affected.
DATA ROM
5
4
3
2
1
WINDOW REGISTER 7 CONTENTS (DWR)
0 PROGRAM SPACE ADDRESS READ 0 DATA SPACE ADDRESS 40h-7Fh IN INSTRUCTION
5 0 1
4
3
2
1
Example:
DWR=28h 0 0 1 0 1 0 0 0 0 1 0 1 1 0 0 1 DATA SPACE ADDRESS 59h
ROM ADDRESS:A19h
0
0
1
0
1
0
0
0
0
1
1
0
0
1
VR01573B
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MEMORY SPACES (Cont'd) 1.3.4 Data RAM/EEPROM/OSD RAM Addressing In all members of the ST638x family 64 bytes of data RAM are directly addressable in the data space from 80h to BFh addresses. The additional 192 bytes of RAM, the 384 bytes of EEPROM, and the OSD RAM can be addressed using the banks of 64 bytes located between addresses 00h and 3Fh. The selection of the bank is done by programming the Data RAM Bank Register (DRBR) located at the E8h address of the Data Space. In this way each bank of RAM, EEPROM or OSD RAM can select 64 bytes at a time. No more than one bank should be set at a time. Data RAM Bank Register (DRBR) Address: E8h - Write only Reset Value: XXh
7 0 DRBR DRBR DRBR DRBR DRBR DRBR DRBR DRBR 7 6 5 4 3 2 1 0
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. Note: Care is required when handling the DRBR as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupts drivers, as the driver cannot save and than restore its previous content. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the DRBR it writes also the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected. Table 5. Data RAM Bank Register Set-up
DRBR Value Hex. Binary 01h 0000 0001 02h 0000 0010 03h 0000 0011 81h 1000 0001 82h 1000 0010 83h 1000 0011 04h 0000 0100 08h 0000 1000 10h 0001 0000 20h 0010 0000 40h 0100 0000 Selection EEPROM Page EEPROM Page EEPROM Page EEPROM Page EEPROM Page EEPROM Page RAM Page 2 RAM Page 3 RAM Page 4 OSD Page 5 OSD Page 6 0 1 2 3 4 5
DRBR7,DRBR1,DRBR0. These bits select the EEPROM pages. DRBR6, DRBR5. Each of these bits, when set, will select one OSD RAM register page. DRBR4,DRBR3,DRBR2. Each of these bits, when set, will select oneRAM page. This register is undefined after reset. Table 5 summarizes how to set the Data RAM Bank Register in order to select the various banks or pages.
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MEMORY SPACES (Cont'd) EEPROM Description The data space of ST638x family from 00h to 3Fh is paged as described in Table 5. 384 bytes of EEPROM located in six pages of 64 bytes (pages 0,1,2,3,4 and 5, see Table 5). Through the programming of the Data RAM Bank Register (DRBR=E8h) the user can select the bank or page leaving unaffected the way to address the static registers. The way to address the "dynamic" page is to set the DRBR as described in Table 5 (e.g. to select EEPROM page 0, the DRBR has to be loaded with content 01h, see Data RAM/EEPROM/OSD RAM addressing for additional information). Bits 0, 1 and 7 of the DRBR are dedicated to the EEPROM. The EEPROM pages do not require dedicated instructions to be accessed in reading or writing. The EEPROM is controlled by the EEPROM Control Register (EECR=EAh). Any EEPROM location can be read just like any other data location, also in terms of access time. To write an EEPROM location takes an average time of 5 ms (10ms max) and during this time the EEPROM is not accessible by the Core. A busy flag can be read by the Core to know the EEPROM status before trying any access. In writing the EEPROM can work in two modes: Byte Mode (BMODE) and Parallel Mode (PMODE). The BMODE is the normal way to use the EEPROM and consists in accessing one byte at a time. The PMODE consists in accessing 8 bytes per time. EEPROM Control Register (EECR) Address: EAh - Read only/Write only Reset Value:
7 SB PS PE BS 0 EN
D7. Not used Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. SB. WRITE ONLY. If this bit is set the EEPROM is disabled (any access will be meaningless) and the
power consumption of the EEPROM is reduced to the leakage values. D5, D4. Reserved for testing purposes, they must be set to zero. PS. WRITE ONLY. Once in Parallel Mode, as soon as the user software sets the PS bit the parallel writing of the 8 adjacent registers will start. PS is internally reset at the end of the programming procedure. Note that less than 8 bytes can be written; after parallel programming the remaining undefined bytes will have no particular content. PE. WRITE ONLY. This bit must be set by the user program in order to perform parallel programming (more bytes per time). If PE is set and the "parallel start bit" (PS) is low, up to 8 adjacent bytes can be written at the maximum speed, the content being stored in volatile registers. These 8 adjacent bytes can be considered as row, whose A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 are the changing bytes. PE is automatically reset at the end of any parallel programming procedure. PE can be reset by the user software before starting the programming procedure, leaving unchanged the EEPROM registers. BS. READ ONLY. This bit will be automatically set by the CORE when the user program modifies an EEPROM register. The user program has to test it before any read or write EEPROM operation; any attempt to access the EEPROM while "busy bit" is set will be aborted and the writing procedure in progress completed. EN. WRITE ONLY. This bit MUST be set to one in order to write any EEPROM register. If the user program will attempt to write the EEPROM when EN= "0" the involved registers will be unaffected and the "busy bit" will not be set. After RESET the content of EECR register will be 00h. Notes: When the EEPROM is busy (BS="1") the EECR can not be accessed in write mode, it is only possible to read BS status. This implies that as long as the EEPROM is busy it is not possible to change the status of the EEPROM control register. EECR bits 4 and 5 are reserved for test purposes, and must never be set to "1".
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MEMORY SPACES (Cont'd) Additional Notes on Parallel Mode. If the user wants to perform a parallel programming the first action should be the setting of the PE bit; from this moment, the first time the EEPROM will be addressed in writing, the ROW address will be latched and it will be possible to change it only at the end of the programming procedure or by resetting PE without programming the EEPROM. After the ROW address latching the Core can "see" just one EEPROM row (the selected one) and any attempt to write or read other rows will produce errors. Do not read the EEPROM while PE is set. As soon as PE bit is set, the 8 volatile ROW latches are cleared. From this moment the user can load data in the whole ROW or just in a subset. PS setting will modify the EEPROM registers corresponding to the ROW latches accessed after PE.
For example, if the software sets PE and accesses EEPROM in writing at addresses 18h,1Ah,1Bh and then sets PS, these three registers will be modified at the same time; the remaining bytes will have no particular content. Note that PE is internally reset at the end of the programming procedure. This implies that the user must set PE bit between two parallel programming procedures. Anyway the user can set and then reset PE without performing any EEPROM programming. PS is a set only bit and is internally reset at the end of the programming procedure. Note that if the user tries to set PS while PE is not set there will not be any programming procedure and the PS bit will be unaffected. Consequently PS bit can not be set if EN is low. PS can be affected by the user set if, and only if, EN and PE bits are also set to one.
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2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 8; the controller being externally linked to both the Reset and Oscillator circuits, while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirectly, for interrupt purposes, through the control registers. 2.2 CPU REGISTERS The ST6 Family CPU core features six registers and three pairs of flags available to the programmer. These are described in the following paragraphs. Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be addressed in Data space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data space. Figure 8. ST6 Core Block Diagram
0,01 TO 8MHz RESET OSCin OSCout
Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in Data space. They are used in the register-indirect addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST6 instruction set can use the indirect registers as any other register of the data space. Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data space as RAM locations at addresses 82h (V) and 83h (W). They can also be accessed using the direct and bit direct addressing modes. Thus, the ST6 instruction set can use the short direct registers as any other register of the data space. Program Counter (PC). The program counter is a 12-bit register which contains the address of the next ROM location to be processed by the core. This ROM location may be an opcode, an operand, or the address of an operand. The 12-bit length allows the direct addressing of 4096 bytes in Program space.
INTERRUPTS CONTROLLER DATA SPACE
OPCODE
FLAG VALUES
CONTROL SIGNALS 2 ADDRESS/READ LINE
DATA RAM/EEPROM
PROGRAM ROM/EPROM ADDRESS 256 DECODER A-DATA B-DATA
DATA ROM/EPROM
DEDICATIONS ACCUMULATOR
12
Program Counter and 6 LAYER STACK
FLAGS ALU RESULTS TO DATA SPACE (WRITE LINE) VR01811
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CPU REGISTERS (Cont'd) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways: - JP (Jump) instruction . . . . . PC=Jump address - CALL instruction . . . . . . . . . PC= Call address - Relative Branch Instruction . PC= PC +/- offset - Interrupt . . . . . . . . . . . . . .PC=Interrupt vector - Reset . . . . . . . . . . . . . . . . . PC= Reset vector - RET & RETI instructions . . . . PC= Pop (stack) - Normal instruction . . . . . . . . . . . . .PC= PC + 1 Flags (C, Z). The ST6 CPU includes three pairs of flags (Carry and Zero), each pair being associated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt mode (CNMI, ZNMI). The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (resp. the NMI flags) instead of the Normal flags. When the RETI instruction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context switching and thus retain their status. The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction; it also participates in the rotate left instruction. The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared. Switching between the three sets of flags is performed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is
automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. Stack. The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. The stack will remain in its "deepest" position if more than 6 nested calls or interrupts are executed, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed. Figure 9. ST6 CPU Programming Mode
l
INDEX REGISTER
b7 b7 b7 b7 b7
X REG. POINTER Y REG. POINTER V REGISTER W REGISTER ACCUMULATOR
b0 SHORT DIRECT ADDRESSING MODE b0 b0 b0 b0 b0
b11
PROGRAM COUNTER
SIX LEVELS STACK REGISTER
NORMAL FLAGS INTERRUPT FLAGS NMI FLAGS
C C C
Z Z Z VA000423
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3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 ON-CHIP CLOCK OSCILLATOR The internal oscillator circuit is designed to require a minimum of external components. A crystal quartz, a ceramic resonator, or an external signal (provided to the OSCin pin) may be used to generate a system clock with various stability/cost tradeoffs. The typical clock frequency is 8MHz. Please note that different frequencies will affect the operation of those peripherals (D/As, SPI) whose reference frequencies are derived from the system clock. The different clock generator connection schemes are shown in Figure 10 and 11. One machine cycle takes 13 oscillator pulses; 12 clock pulses are needed to increment the PC while and additional 13th pulse is needed to stabilize the internal latches during memory addressing. This means that with a clock frequency of 8MHz the machine cycle is 1.625Sec. The crystal oscillator start-up time is a function of many variables: crystal parameters (especially RS), oscillator load capacitance (CL), IC parameters, ambient temperature, and supply voltage.It must be observed that the crystal or ceramic leads and circuit connections must be as short as possible. Typical values for CL1 and CL2 are in the range of 15pF to 22pF but these should be chosen based on the crystal manufacturers specification. Typical input capacitance for OSCin and OSCout pins is 5pF. The oscillator output frequency is internally divided by 13 to produce the machine cycle and by 12 to produce the Timers and the Watchdog clock. A byte cycle is the smallest unit needed to execute any operation (i.e., increment the program counter). An instruction may need two, four, or five byte cycles to be executed (See Table 6). Table 6. Instruction Timing with 8MHz Clock
Instruction Type Branch if set/reset Branch & Subroutine Branch Bit Manipulation Load Instruction Arithmetic & Logic Conditional Branch Program Control Cycles 5 Cycles 4 Cycles 4 Cycles 4 Cycles 4 Cycles 2 Cycles 2 Cycles Execution Time 8.125s 6.50s 6.50s 6.50s 6.50s 3.25s 3.25s
Figure 10. Clock Generator Option 1
CRYSTAL/RESONATOR CLOCK
ST6xxx
OSCin
OSCout
CL1
CL2 VA0016B
Figure 11. Clock Generator Option 2
EXTERNAL CLOCK
ST6xxx
OSCin
OSCout NC VA0015C
Figure 12. OSCin, OSCout Diagram
OSCin, OSCout (QUARTZ PINS) VDD OSCin
1M
VDD OSCout
VA00462
In
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3.2 RESETS The MCU can be reset in three ways: - by the external Reset input being pulled low; - by Power-on Reset; - by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required. The RESET pin may be pulled low in RUN, WAIT or STOP mode. This input can be used to reset the MCU internal state and ensure a correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal Reset signal is generated by adding a delay to the external signal. Therefore even short pulses on the RESET pin are acceptable, provided VDD has completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the RESET pin is held low. If RESET activation occurs in RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the Inputs and Outputs are configured as inputs with pull-up resistors if available. When the level on the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period. If RESET pin activation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs are configured as inputs with pull-up resistors if available. When the level of the RESET pin then goes high, the initialization sequence is executed following expiry of the internal delay period. 3.2.2 Power-on Reset The function of the POR circuit consists in waking up the MCU at an appropriate stage during the power-on sequence. At the beginning of this sequence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up resistors and no instruction is executed. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence is executed immediately following the internal delay. The internal delay is generated by an on-chip counter. The internal reset line is released 2048 internal clock cycles after release of the external reset. The internal POR device is a static mechanism which forces the reset state when VDD is below a threshold voltage in the range 3.4 to 4.2 Volts (see Figure 13). The circuit guarantees that the MCU will exit or enter the reset state correctly, without spurious effects, ensuring, for example, that EEPROM contents are not corrupted. Note: This feature is not available on OTP/EPROM Devices. Figure 13. Power ON/OFF Reset operation
VDD 4.2 Threshold 3.4
t
VDD POWER ON/OFF RESET
t
VR02037
Figure 14. Reset and Interrupt Processing
RESET
NMI MASK SET INT LATCH CLEARED ( IF PRESENT )
SELECT NMI MODE FLAGS
PUT FFEH ON ADDRESS BUS
YES
IS RESET STILL PRESENT?
NO
LOAD PC FROM RESET LOCATIONS FFE/FFF
FETCH INSTRUCTION VA000427
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RESETS (Cont'd) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst other things, resets the watchdog counter. The MCU restarts just as though the Reset had been generated by the RESET pin, including the built-in stabilisation delay period. 3.2.4 Application Note No external resistor is required between VDD and the Reset pin, thanks to the built-in pull-up device. 3.2.5 MCU Initialization Sequence When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (located in program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a Reset, the Interrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode; this prevents the initialisation routine from being interrupted. The initialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal Figure 16. Reset Circuit
mode and enable interrupts. If no pending interrupt is present at the end of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETI instruction. If, however, a pending interrupt is present, it will be serviced. Figure 15. Reset and Interrupt Processing
RESET
JP RESET VECTOR
JP:2 BYTES/4 CYCLES
INITIALIZATION ROUTINE RETI
RETI: 1 BYTE/2 CYCLES
VA00181
OSCILLATOR SIGNAL COUNTER RESET (ACTIVE LOW) 1k VDD 300k WATCHDOG RESET POWER ON/OFF RESET TO ST6 RESET
ST6 INTERNAL RESET
VA0200E
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3.3 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION The hardware activated digital watchdog function consists of a down counter that is automatically initialized after reset so that this function does not need to be activated by the user program. As the watchdog function is always activated this down counter can not be used as a timer. The watchdog is using one data space register (HWDR location D8h). The watchdog register is set to FEh on reset and immediately starts to count down, requiring no software start. Similarly the hardware activated watchdog can not be stopped or delayed by software. The watchdog time can be programmed using the 6 MSBs in the watchdog register, this gives the possibility to generate a reset in a time between 3072 to 196608 oscillator cycles in 64 possible steps. (With a clock frequency of 8MHz this means from 384ms to 24.576ms). The reset is prevented if the register is reloaded with the desired value before bits 2-7 decrement from all zeros to all ones. The presence of the hardware watchdog deactivates the STOP instruction and a WAIT instruction is automatically executed instead of a STOP. Bit 1 of the watchdog register (set to one at reset) can be used to generate a software reset if cleared to zero). Figure 17 shows the watchdog block diagram while Figure 18 shows its working principle.
Figure 17. Hardware Activated Watchdog Block Diagram
RESET
Q RSFF S R
-2
7
DB1.7 LOAD SET
-2 8 SET
-12
DB0
8
OSCILLATOR CLOCK
WRITE RESET DATA BUS
VA00010
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HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION (Cont'd) Figure 18. Hardware Activated Watchdog Hardware Activated Watchdog Register (HWDR) Working Principle Address: D8h - Read/Write Reset Value: 0FEh
D0
7 T1 T2 T3 T4 T5 T6 SR 0 C
BIT7
D1 WATCHDOG CONTROL REGISTER
BIT6
T1-T6. These are the watchdog counter bits. It should be noted that D7 (T1) is the LSB of the counter and D2 (T6) is the MSB of the counter, these bits are in the opposite order to normal. SR. This bit is set to one during the reset phase and will generate a software reset if cleared to zero. C. This is the watchdog activation bit that is hardware set. The watchdog function is always activated independently of changes of value of this bit. The register reset value is FEh (Bit 1-7 set to one, Bit 0 cleared).
D2
BIT5
RESET
D3
BIT4
D4
BIT3
D5
BIT2
D6
BIT1
D7
BIT0
8-BIT
DOWN COUNTER
OSC-12
VA00190
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3.4 INTERRUPT The ST638x Core can manage 4 different maskable interrupt sources, plus one non-maskable interrupt source (top priority level interrupt). Each source is associated with a particular interrupt vector that contains a Jump instruction to the related interrupt service routine. Each vector is located in the Program Space at a particular address (see Table 7). When a source provides an interrupt request, and the request processing is also enabled by the ST638x Core, then the PC register is loaded with the address of the interrupt vector (i.e. of the Jump instruction). Finally, the PC is loaded with the address of the Jump instruction and the interrupt routine is processed. The relationship between vector and source and the associated priority is hardware fixed for the different ST638x devices. For some interrupt sources it is also possible to select by software the kind of event that will generate the interrupt. All interrupts can be disabled by writing to the GEN bit (global interrupt enable) of the interrupt option register (address C8h). After a reset, ST638x is in non maskable interrupt mode, so no interrupts will be accepted and NMI flags will be used, until a RETI instruction is executed. If an interrupt is executed, one special cycle is made by the core, during that the PC is set to the related interrupt vector address. A jump instruction at this address has to redirect program execution to the beginning of the related interrupt routine. The interrupt detecting cycle, also resets the related interrupt flag (not available to the user), so that another interrupt can be stored for this current vector, while its driver is under execution. If additional interrupts arrive from the same source, they will be lost. NMI can interrupt other interrupt routines at any time, while other interrupts cannot interrupt each other. If more than one interrupt is waiting for service, they are executed according to their priority. The lower the number, the higher the priority. Priority is, therefore, fixed. Interrupts are checked during the last cycle of an instruction (RETI included). Level sensitive interrupts have to be valid during this period. 3.4.1 Interrupt Vectors/Sources The ST638x Core includes 5 different interrupt vectors in order to branch to 5 different interrupt routines. The interrupt vectors are located in the fixed (or static) page of the Program Space. The interrupt vector associated with the nonmaskable interrupt source is named interrupt vector #0. It is located at the (FFCh,FFDh) addresses in the Program Space. This vector is associated with the PC6/IRIN pin. The interrupt vectors located at addresses (FF6h, FF7h), (FF4h, FF5h), (FF2h, FF3h), (FF0h, FF1h) are named interrupt vectors #1, #2, #3 and #4 respectively. These vectors are associated with TIMER 2 (#1), VSYNC (#2), TIMER 1 (#3) and PC4(PWRIN) (#4). Table 7. Interrupt Vectors/Sources Relationships
Interrupt Source PC6/IRIN Pin 1 Timer 2 Vsync Timer 1 PC4/PWRIN Associated Vector Interrupt Vector # 0 (NMI) Interrupt Vector # 1 Interrupt Vector #2 Interrupt Vector #3 Interrupt Vector #4 Vector Address 0FFCh-0FFDh 0FF6h-0FF7h 0FF4h-0FF5h 0FF2h-0FF3h 0FF0h-0FF1h
Note 1. This pin is associated with the NMI Interrupt Vector 3.4.2 Interrupt Priority The non-maskable interrupt request has the highest priority and can interrupt any other interrupt routines at any time, nevertheless the other interrupts cannot interrupt each other. If more than one interrupt request is pending, they are processed by the ST638x Core according to their priority level: vector #1 has the higher priority while vector #4 the lower. The priority of each interrupt source is hardware fixed.
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INTERRUPTS (Cont'd) 3.4.3 Interrupt Option Register Interrupt Option Register (IOR) Address: (C8h) - Write only Reset Value: X000XXXXb
7 0
EL1
ES2
GEN
-
-
-
-
The Interrupt Option Register (IOR register, location C8h) is used to enable/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register can be addressed in the Data Space as RAM location at the C8h address, nevertheless it is a write-only register that can not be accessed with single-bit operations. The operating modes of the external interrupt inputs associated to interrupt vectors #1 and #2 are selected through bits 5 and 6 of the IOR register. Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7. Not used. EL1. This is the Edge/Level selection bit of interrupt #1. When set to one, the interrupt is generated on low level of the related signal; when cleared to zero, the interrupt is generated on falling edge. The bit is cleared to zero after reset. ES2. This is the edge selection bit on interrupt #2. This bit is used on the ST638x devices with onchip OSD generator for VSYNC detection. When this bit is se to one, the interrupt #2 is positive edge sensitive, when cleared to zero the negative edge sensitive interrupt is selected. GEN. This is the global enable bit. When set to one all interrupts are globally enabled; when this bit is cleared to zero all interrupts are disabled (excluding NMI). D3 - D0. These bits are not used. 3.4.4 Interrupt Procedure The interrupt procedure is very similar to a call procedure; the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event the user does not know about the context and the time at which it occurred. As a result the user should save all the data space registers which will be used inside the interrupt routines. There are separate sets of processor flags for normal, interrupt and non-maskable interrupt modes which are automatically switched and so these do not need to be saved.
The following list summarizes the interrupt procedure (refer also to Figure 19*) - Interrupt detection - The flags C and Z of the main routine are exchanged with the flags C and Z of the interrupt routine (resp. the NMI flags) - The value of the PC is stored in the first level of the stack - The normal interrupt lines are inhibited (NMI still active) - The edge flip-flop is reset - The related interrupt vector is loaded in the PC. - User selected registers are saved inside the interrupt service routine (normally on a software stack) - The source of the interrupt is found by polling (if more than one source is associated to the same vector) - Interrupt servicing - Return from interrupt (RETI) - Automatically the ST638x core switches back to the normal flags (resp the interrupt flags) and pops the previous PC value from the stack Figure 19. Interrupt Processing Flow-Chart
INSTRUCTION
FETCH INSTRUCTION
EXECUTE INSTRUCTION
NO WAS THE INSTRUCTION A RETI ? YES YES
LOAD PC FROM INTERRUPT VECTOR (FFC/FFD)
?
NO
IS THE CORE ALREADY IN NORMAL MODE?
SET INTERRUPT MASK
CLEAR INTERRUPT MASK
PUSH THE PC INTO THE STACK
SELECT PROGRAM FLAGS
SELECT INTERNAL MODE FLAG
"POP" THE STACKED PC
NO
?
YES
CHECK IF THERE IS AN INTERRUPT REQUEST AND INTERRUPT MASK
VA000014
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INTERRUPTS (Cont'd) The interrupt routine begins usually by the identification of the device that has generated the interrupt request. The user should save the registers which are used inside the interrupt routine (that holds relevant data) into a software stack. After the RETI instruction execution, the Core carries out the previous actions and the main routine can continue. 3.4.5 ST638x Interrupt Details IR Interrupt (#0). The IRIN/PC6 Interrupt is connected to the first interrupt #0 (NMI, 0FFCh). If the IRINT interrupt is disabled at the Latch circuitry, then it will be high. The #0 interrupt input detects a high to low level. Note that once #0 has been latched, then the only way to remove the latched #0 signal is to service the interrupt. #0 can interrupt the other interrupts. A simple latch is provided from the PC6(IRIN) pin in order to generate the IRINT signal. This latch can be triggered by either the positive or negative edge of IRINT signal. IRINT is inverted with respect to the latch. The latch can be read by software and reset by software. TIMER 2 Interrupt (#1). The TIMER 2 Interrupt is connected to the interrupt #1 (0FF6h). The TIMER 2 interrupt generates a low level (which is latched in the timer). Only the low level selection for #1 can be used. Bit 6 of the interrupt option register C8h has to be set. VSYNC Interrupt (#2). The VSYNC Interrupt is connected to the interrupt #2. When disabled the VSYNC INT signal is low. The VSYNC INT signal is inverted with respect to the signal applied to the VSYNC pin. Bit 5 of the interrupt option register C8h is used to select the negative edge (ES2=0) or the positive edge (ES2=1); the edge will depend on the application. Note that once an edge has been latched, then the only way to remove the
latched signal is to service the interrupt. Care must be taken not to generate spurious interrupts. This interrupt may be used to synchronize the VSYNC signal in order to change characters in the OSD only when the screen is on vertical blanking (if desired). This method may also be used to blink characters. TIMER 1 Interrupt (#3). The TIMER 1 Interrupt is connected to the fourth interrupt #3 (0FF2h) which detects a low level (latched in the timer). PWR Interrupt (#4). The PWR Interrupt is connected to the fifth interrupt #4 (0FF0h). If the PWRINT is disabled at the PWR circuitry, then it will be high. The #4 interrupt input detects a low level. A simple latch is provided from the PC4 (PWRIN)pin in order to generate the PWRINT signal. This latch can be triggered by either the positive or negative edge of the PWRIN signal. PWRINT is inverted with respect to the latch. The latch can be reset by software. Notes: Global disable does not reset edge sensitive interrupt flags. These edge sensitive interrupts become pending again when global disabling is released. Moreover, edge sensitive interrupts are stored in the related flags also when interrupts are globally disabled, unless each edge sensitive interrupt is also individually disabled before the interrupting event happens. Global disable is done by clearing the GEN bit of Interrupt option register, while any individual disable is done in the control register of the peripheral. The on-chip Timer peripherals have an interrupt request flag bit (TMZ), this bit is set to one when the device wants to generate an interrupt request and a mask bit (ETI) that must be set to one to allow the transfer of the flag bit to the Core.
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3.5 POWER SAVING MODES STOP and WAIT modes have been implemented in the ST638x in order to reduce the current consumption of the device during idle periods. These two modes are described in the following paragraphs. Since the hardware activated digital watchdog function is present, the STOP instruction is de-activated and any attempt to execute it will cause the automatic execution of a WAIT instruction. 3.5.1 WAIT Mode The configuration of the MCU in the WAIT mode occurs as soon as the WAIT instruction is executed. The microcontroller can also be considered as being in a "software frozen" state where the Core stops processing the instructions of the routine, the contents of the RAM locations and peripheral registers are saved as long as the power supply voltage is higher than the RAM retention voltage but where the peripherals are still working. The WAIT mode is used when the user wants to reduce the consumption of the MCU when it is in idle, while not losing count of time or monitoring of external events. The oscillator is not stopped in order to provide clock signal to the peripherals. The timers counting may be enabled (writing the PSI bit in TSCR1 register) and the timer interrupt may be also enabled before entering the WAIT mode; this allows the WAIT mode to be left when timer interrupt occurs. If the exit from the WAIT mode is performed with a general RESET (either from the activation of the external pin or by watchdog reset) the MCU will enter a normal reset procedure as described in the RESET chapter. If an interrupt is generated during WAIT mode the MCU behaviour depends on the state of the MCU Core before the initialization of the WAIT sequence, but also of the kind of the interrupt request that is generated. This case will be described in the following paragraphs. In any case, the MCU Core does not generate any delay after the occurrence of the interrupt because the oscillator clock is still available. 3.5.2 STOP Mode Since the hardware activated watchdog is present on the ST638x, the STOP instruction has been deactivated. Any attempt to execute a STOP instruction will cause a WAIT instruction to be executed instead. 3.5.3 Exit from WAIT Mode The following paragraphs describe the output procedure of the MCU Core from WAIT mode when an interrupt occurs. It must be noted that the restart sequence depends on the original state of the MCU (normal, interrupt or non-maskable interrupt mode) before the start of the WAIT sequence, but also of the type of the interrupt request that is generated. In all cases the GEN bit of IOR has to be set to 1 in order to restart from WAIT mode. Contrary to the operation of NMI in the run mode, the NMI is masked in WAIT mode if GEN=0. Normal Mode. If the MCU Core was in the main routine when the WAIT instruction has been executed, the Core exits from WAIT mode as soon as an interrupt occurs; the corresponding interrupt routine is executed, and at the end of the interrupt service routine, the instruction that follows the WAIT instruction is executed if no other interrupts are pending. Non-maskable Interrupt Mode. If the WAIT instruction has been executed during the execution of the non-maskable interrupt routine, the MCU Core outputs from WAIT mode as soon as any interrupt occurs: the instruction that follows the WAIT instruction is executed and the MCU Core is still in the non-maskable interrupt mode even if another interrupt has been generated. Normal Interrupt Mode. If the MCU Core was in the interrupt mode before the initialization of the WAIT sequence, it outputs from the wait mode as soon as any interrupt occurs. Nevertheless, two cases have to be considered: - If the interrupt is a normal interrupt, the interrupt routine in which the WAIT was entered will be completed with the execution of the instruction that follows the WAIT and the MCU Core is still in the interrupt mode. At the end of this routine pending interrupts will be serviced in accordance to their priority. - If the interrupt is a non-maskable interrupt, the non-maskable routine is processed at first. Then, the routine in which the WAIT was entered will be completed with the execution of the instruction that follows the WAIT and the MCU Core is still in the normal interrupt mode. Notes: If all the interrupt sources are disabled, the restart of the MCU can only be done by a Reset activation. The Wait instruction is not executed if an enabled interrupt request is pending. In ST638x devices, the hardware activated digital watchdog function is present. As the watchdog is always activated, the STOP instruction is de-activated and any attempt to execute the STOP instruction will cause an execution of a WAIT instruction.
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4 ON-CHIP PERIPHERALS
4.1 I/O PORTS The ST638x microcontrollers use three standard I/ O ports (A,B,C) with up to eight pins on each port; refer to the device pin configurations to see which pins are available. Each line can be individually programmed either in the input mode or the output mode as follows by software. - Output - Input with on-chip pull-up resistor (selected by software) - Input without on-chip pull-up resistor (selected by software) Note: pins with 12V open-drain capability do not have pull-up resistors. In output mode the following hardware configurations are available: - Open-drain output 12V (PA4-PA7, PC4-PC7) - Open-drain output 5V (PC0-PC3) - Push-pull output (PA0-PA3, PB0-PB6) The lines are organized in three ports (port A,B,C). The ports occupy 6 registers in the data space. Each bit of these registers is associated with a particular line (for instance, the bits 0 of the Port A Data and Direction registers are associated with the PA0 line of Port A). There are three Data registers (DRA, DRB, DRC), that are used to read the voltage level values of the lines programmed in the input mode, or to write the logic value of the signal to be output on the lines configured in the output mode. The port Data Registers can be read to get the effective logic levels of the pins, but they can be also written by the user software, in conjunction with the related Data Direction Register, to select the different input mode options. Single-bit operations on I/O registers (bit set/reset instructions) are possible but care is necessary because reading in input mode is made from I/O pins and therefore might be influenced by the external load, while writing will directly affect the Port data register causing an undesired changes of the input configuration. The three Data Direction registers (DDRA, DDRB, DDRC) allow the selection of the direction of each pin (input or output). All the I/O registers can be read or written as any other RAM location of the data space, so no extra RAM cell is needed for port data storing and manipulation. During the initialization of the MCU, all the I/O registers are cleared and the input mode with pull-up is selected on all the pins thus avoiding pin conflicts (with the exception of PC2 that is set in output mode and is set high i.e. high impedance).
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I/O PORTS (Cont'd) 4.1.1 Details of I/O Ports When programmed as an input a pull-up resistor (if available) can be switched active under program control. When programmed as an output the I/O port will operate either in the push-pull mode or the open-drain mode according to the hardware fixed configuration as specified below. Port A. PA0-PA3 are available as push-pull when outputs. PA4-PA7 are available as open-drain (no push-pull programmability) capable of withstanding 12V (no resistive pull-up in input mode). PA6PA7 has been specially designed for higher driving capability and are able to sink 25mA with a maximum VOL of 1V. Port B. All lines are configured as push-pull when outputs. Port C. PC0-PC3 are available as open-drain capable of withstanding a maximum VDD+0.3V. PC4-PC7 are avail-able as open-drain capable of withstanding 12V (no resistive pull-up in input mode). Some lines are also used as I/O buffers for signals coming from the on-chip SPI.
In this case the final signal on the output pin is equivalent to a wired AND with the programmed data output. If the user needs to use the serial peripheral, the I/ O line should be set in output mode while the open-drain configuration is hardware fixed; the corresponding data bit must set to one. If the latched interrupt functions are used (IRIN, PWRIN) then the corresponding pins should be set to input mode. On ST638x the I/O pins with double or special functions are: - PC0/SCL (connected to the SPI clock signal) - PC1/SDA (connected to the SPI data signal) - PC3/SEN (connected to the SPI enable signal) - PC4/PWRIN (connected to the PWRIN interrupt latch) - PC6/IRIN (connected to the IRIN interrupt latch) All the Port A,B and C I/O lines have Schmitt-trigger input configuration with a typical hysteresis of 1V.
Table 8. I/O Port Options Selection (Ports A and B only)
DDR 0 0 1 DR 0 1 X Mode Input Input Output Option With on-chip pull-up resistor Without on-chip pull-up resistor Output open-drain or push-pull
Note X: Means don't care.
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I/O PORTS (Cont'd) Table 9. I/O Port Option Selections
MODE AVAILABLE ON(1)
VDD
SCHEMATIC
PA0-PA7 Input PB0-PB2 PB4-PB6 PC0-PC7 Data in
PA0-PA3 Input with pull up PB0-PB2 PB4-PB6 PC0-PC3
VDD
Data in
Open drain output 5V Open drain output 5mA / 12V
PC0-PC3 PA4-PA7 PC4-PC7 Data out
Push-pull output 5mA Push-pull output 10mA
PB0-PB2 PB4-PB6 PA0-PA3
VDD
VDD
Data out
Note 1. Provided the correct configuration has been selected.
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I/O PORTS (Cont'd) 4.1.2 I/O Pin Programming Each pin can be individually programmed as input or output with different input and output configurations. This is achieved by writing to the relevant bit in the data (DR) and data direction register (DDR). Table 10 shows all the port configurations that can be selected by the user software. 4.1.3 Input/Output Configurations The Table 9 shows the I/O lines hardware configuration for the different options. Notes: The WAIT instruction allows the ST638x to be used in situations where low power consumption is needed. This can only be achieved however if the I/O pins either are programmed as inputs with well defined logic levels or have no power consuming resistive loads in output mode. As the same die is used for the different ST638x versions the unavailable I/O lines of ST638x should be programmed in output mode. Single-bit operations on I/O registers are possible but care is necessary because reading in input mode is made from I/O pins while writing will directly affect the Port data register causing an undesired changes of the input configuration. Table 10. I/O Port Options Selection (Port C)
DDR 0 0 1 DR 0 1 X Mode Option Input With on-chip pull-up resistor Input Without on-chip pull-up resistor Output Open-drain
4.1.4 I/O Port Registers 4.1.4.1 Data Registers Ports A, B, C Data Register Address: C0h (PA), C1h (PB), C2h (PC) - Read/ Write Reset Value: 00h
7 PA/ PB/ PC7 PA/ PB/ PC6 PA/ PB/ PC5 PA/ PB/ PC4 PA/ PB/ PC3 PA/ PB/ PC2 PA/ PB/ PC1 0 PA/ PB/ PC0
PA7-PA0. These are the I/O port A data bits. Reset at power-on. PB7-PB0. These are the I/O port B data bits. Reset at power-on. PC7-PC0. Set to 04h at power-on. Bit 2 (PC2 pin) is set to one (open drain therefore high impedance). 4.1.4.2 Data Direction Registers Port A, B, C Data Direction Register Address: C4h (PA), C5h (PB), C6h (PC) - Read/ Write Reset value:00h
7 PA/ PB/ PC7 PA/ PB/ PC6 PA/ PB/ PC5 PA/ PB/ PC4 PA/ PB/ PC3 PA/ PB/ PC2 PA/ PB/ PC1 0 PA/ PB/ PC0
Note: X. Means don't care.
PA7-PA0. These are the I/O port A data direction bits. When a bit is cleared to zero the related I/O line is in input mode, if bit is set to one the related I/O line is in output mode. Reset at power-on. PB7-PB0. These are the I/O port B data direction bits. When a bit is cleared to zero the related I/O line is in input mode, if bit is set to one the related I/O line is in output mode. Reset at power-on. PC7-PC0. These are the I/O port C data direction bits. When a bit is cleared to zero the related I/O line is in input mode, if bit is set to one the related I/O line is in output mode. Set to 04h at power-on. Bit 2 (PC2 pin) is set to one (output mode selected).
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4.2 TIMERS The ST638x devices offer two on-chip Timer peripherals consisting of an 8-bit counter with a 7-bit programmable prescaler, thus giving a maximum count of 215, and a control logic that allows configuration the peripheral operating mode. Figure 20 shows the Timer block diagram. The content of the 8-bit counters can be read/written in the Timer/ Counter registers TCR that are addressed in the data space as RAM locations at addresses D3h (Timer 1), DBh (Timer 2). The state of the 7-bit prescaler can be read in the PSC register at addresses D2h (Timer 1) and DAh (Timer 2). The control logic is managed by TSCR registers at D4h (Timer 1) and DCh (Timer 2) addresses as described in the following paragraphs. The following description applies to all Timers. The 8-bit counter is decrement by the output (rising edge) coming from the 7-bit prescaler and can be loaded and read under program control. When it decrements to zero then the TMZ (timer zero) bit in the TSCR is set to one. If the ETI (enable timer interrupt) bit in the TSCR is also set to one an interrupt request, associated to interrupt vector #3 for Timer 1 and #1 for Timer 2, is generated. The interrupt of the timer can be used to exit the MCU from the WAIT mode. Figure 20. Timer Peripheral Block Diagram The prescaler decrements on rising edge. The prescaler input is the oscillator frequency divided by 12. Depending on the division factor programmed by PS2/PS1/PS0 (see Table 11) bits in the TSCR, the clock input of the timer/counter register is multiplexed to different sources. On division factor 1, the clock input of the prescaler is also that of timer/counter; on factor 2, bit 0 of prescaler register is connected to the clock input of TCR. This bit changes its state with the half frequency of prescaler clock input. On factor 4, bit 1 of PSC is connected to clock input of TCR, and so on. On division factor 128, the MSB bit 6 of PSC is connected to clock input of TCR. The prescaler initialize bit (PSI) in the TSCR register must be set to one to allow the prescaler (and hence the counter) to start. If it is cleared to zero then all of the prescaler bits are set to one and the counter is inhibited from counting.The prescaler can be given any value between 0 and 7Fh by writing to the related register address, if bit PSI in the TSCR register is set to one. The tap of the prescaler is selected using the PS2/PS1/PS0 bits in the control register. Figure 21 illustrates the Timer working principle.
DATABUS 8 8 6 5 4 3 2 1 0 8 8-BIT COUNTER
b7 b6 b5 b4
8
b3 b2 b1 b0
PSC
SELECT 1 OF 8
STATUS/CONTROL REGISTER
TMZ ETI TOUT DOUT PSI PS2 PS1 PS0
3
TIMER INTERRUPT LINE SYNCHRONIZATION LOGIC LATCH
fOSC
:12
VA00009
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TIMERS (Cont'd) 4.2.1 Timer Operating Modes Since in the ST638x devices the external TIMER pin is not connected, the only allowed operating mode is the output mode, which is selected by setting bit 4 and by clearing bit 5 in the TSCR1 register. This procedure will enable Timer 1 and Timer 2. Output Mode (TSCR1 D4 = 1, TSCR1 D5 = 0). On this mode the timer prescaler is clocked by the prescaler clock input (OSC/12). The user can select the desired prescaler division ratio through the PS2/PS1/PS0 bits. When TCR count reaches 0, it sets the TMZ bit in the TSCR. The TMZ bit can be tested under program control to perform timer functions whenever it goes high. Bits D4 and D5 on TSCR2 (Timer 2) register are not implemented. Timer Interrupt When the counter register decrements to zero and the software controlled ETI (enable timer interrupt) bit is set to one then an interrupt request associated to interrupt vector #3 (for Timer 1), to interrupt Figure 21. Timer Working Principle
vector #1 (for Timer 2) is generated. When the counter decrements to zero also the TMZ bit in the TSCR register is set to one. Notes: TMZ is set when the counter reaches 00h; however, it may be set by writing 00h in the TCR register or setting the bit 7 of the TSCR register. TMZ bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service routine. After reset, the 8-bit counter register is loaded to FFh while the 7-bit prescaler is loaded to 7Fh, and the TSCR register is cleared which means that timer is stopped (PSI=0) and timer interrupt disabled. A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i.e. if a write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter reaches 00h again. The values of the TCR and the PSC registers can be read accurately at any time.
7-BIT PRESCALER CLOCK BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6
0
1
2
4 3 8-1 MULTIPLEXER
5
6
7
PS0 PS1 PS2
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
8-BIT COUNTER
VA00186
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TIMERS (Cont'd) 4.2.2 Timer Status Control Registers (TSCR) Timers 1 and 2 Address: D4h (Timer 1), DCh (Timer 2) - Read/ Write Reset Value: 00h
7 TMZ ETI D5 D4 PSI PS2 PS1 0 PS0
written in TSCR1 by user's software to enable the operation of Timer 1 and 2. Table 11. Prescaler Division Factors
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 Divided By 1 2 4 8 16 32 64 128
TMZ. Low-to-high transition indicates that the timer count register has decremented to zero. This bit must be cleared by user software before to start with a new count. ETI. This bit, when set, enables the timer interrupt (vector #3 for Timer 1, vector #2 for Timer 2 request). If ETI=0 the timer interrupt is disabled. If ETI= 1 and TMZ= 1 an interrupt request is generated. D5. This is the timers enable bit D5. It must be cleared to 0 together with a set to 1 of bit D4 to enable Timer 1 and Timer 2 functions. It is not implemented on registers TSCR2. D4. This is the timers enable bit D4. This bit must be set to 1 together with a clear to 0 of bit D5 to enable all Timers (Timer 1 and 2) functions. It is not implemented on registers TSCR2.
D5 0 0 1 D4 0 1 X Timers Disabled Enabled Reserved
4.2.3 Timer Counter Registers (TCR) Timer Counter 1 and 2 Address: D3h (Timer Counter 1), DBh (Timer Counter 2) - Read/Write Reset Value: FFh
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7-0 = D7-D0: Counter Bits. 4.2.4 Timer Prescaler Registers (PSCR) Timer Prescalers 1 and 2 Address: D2h (Timer Prescaler 1), DAh (Timer Prescaler 2) - Read/Write Reset Value: 7Fh
7 D7 D6 D5 D4 D3 D2 D1 0 D0
PSI. Used to initialize the prescaler and inhibit its counting while PSI = 0 the prescaler is set to 7Fh and the counter is inhibited. When PSI = 1 the prescaler is enabled to count downwards. As long as PSI= 0 both counter and prescaler are not running. PS2-PS0. These bits select the division ratio of the prescaler register. (see Table 11) The TSCR1 and TSCR2 registers are cleared on reset. The correct D4-D5 combination must be
Bit 7 = D7: Always read as "0". Bit 6-0 = D6-D0: Prescaler Bits.
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4.3 SERIAL PERIPHERAL INTERFACE The ST638x Serial Peripheral Interface (SPI) has been designed to be cost effective and flexible in interfacing the various peripherals in TV applications. It maintains the software flexibility but adds hardware configurations suitable to drive devices which require a fast exchange of data. The three pins dedicated for serial data transfer (single master only) can operate in the following ways: - as standard I/O lines (software configuration) - as S-BUS or as I2C BUS (two pins) - as standard (shift register) SPI When using the hardware SPI, a fixed clock rate of 62.5kHz is provided. It has to be noted that the first bit that is output on the data line by the 8-bit shift register is the MSB. 4.3.1 S-BUS/I2C BUS Protocol Information The S-BUS is a three-wire bidirectional data-bus with functional features similar to the I2C BUS. In fact the S-BUS includes decoding of Start/Stop conditions and the arbitration procedure in case of multimaster system configuration (the ST638x SPI allows a single-master only operation). The SDA line, in the I2C BUS represents the AND combination of SDA and SEN lines in the S-BUS. If the SDA and the SEN lines are short-circuit connected, they appear as the SDA line of the I2C BUS. The Start/Stop conditions are detected (by the external peripherals suited to work with S-BUS/I2C BUS) in the following way: - On S-BUS by a transition of the SENline (1 to 0 Start, 0 to 1 Stop) while the SCL line is at high level. - On I2C BUS by a transition of the SDA line (10 Start, 01Stop) while the SCL line is at high level. Start and Stop condition are always generated by the master (ST638x SPI can only work as single master). The bus is busy after the start condition and can be considered again free only when a certain time delay is left after the stop condition. In the S-BUS configuration the SDA line is only allowed to change during the time SCL line is low. After the start information the SENline returns to high level and re-mains unchanged for all the data transmission time. When the transmission is completed the SDA line is set to high level and, at the same time, the SEN line returns to the low level in order to supply the stop in-formation with a low to high transition, while the SCL line is at high level. On the SBUS, as on the I2C BUS, each eight bit information (byte) is followed by one acknowledged bit which is a high level put on the SDA line by the transmitter. A peripheral that acknowledges has to pull down the SDA line during the acknowledge clock pulse. An addressed receiver has to generate an acknowledge after the reception of each byte; otherwise the SDA line remains at the high level during the ninth clock pulse time. In this case the master transmitter can generate the Stop condition, via the SEN (or SDA in I2C BUS) line, in order to abort the transfer.
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SERIAL PERIPHERAL INTERFACE (Cont'd) Start/Stop Acknowledge. The timing specs of the S-BUS protocol require that data on the SDA (only on this line for I2C BUS) and SEN lines be stable during the "high" time of SCL. Two exceptions to this rule are foreseen and they are used to signal the start and stop condition of data transfer. - On S-BUS by a transition of the SEN line (10 Start, 01 Stop) while the SCL line is at high level. - On I2C BUS by a transition of the SDA line (10 Start, 01 Stop) while the SCL line is at high level. Data are transmitted in 8-bit groups; after each group, a ninth bit is interposed, with the purpose of acknowledging the transmitting sequence (the transmit device place a "1" on the bus, the acknowledging receiver a "0"). Interface Protocol. This paragraph deals with the description of data protocol structure. The interface protocol includes: - A start condition - A "slave chip address" byte, transmitted by the master, containing two different information: a. the code identifying the device the master wants to address (this information is present in the first seven bits) b. the direction of transmission on the bus (this information is given in the 8th bit of the byte); "0" means "Write", that is from the master to the slave, while "1" means "Read". The addressed slave must always acknowledge. The sequence from, now on, is different according to the value of R/W bit. 1. R/W = "0" (Write) In all the following bytes the master acts as transmitter; the sequence follows with:
a. an optional data byte to address (if needed) the slave location to be written (it can be a word address in a memory or a register address, etc.). b. a "data" byte which will be written at the address given in the previous byte. c. further data bytes. d. a STOP condition A data transfer is always terminated by a stop condition generated from the master. The ST638x peripheral must finish with a stop condition before another start is given. Figure 22 shows an example of write operation. 2. R/W = "1" (Read) In this case the slave acts as transmitter and, therefore, the transmission direction is changed. In read mode two different conditions can be considered: a. The master reads slave immediately after first byte. In this case after the slave address sent from the master with read condition enabled the master transmitter becomes master receiver and the slave receiver becomes slave transmitter. b. The master reads a specified register or location of the slave. In this case the first sent byte will contain the slave address with write condition enabled, then the second byte will specify the address of the register to be read. At this moment a new start is given together with the slave address in read mode and the procedure will proceed as described in previous point "a".
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 22. IC Master Transmit to Slave Receiver (Write Mode)
ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE MSB S SLAVE ADDRESS O A WORD ADDRESS A DATA A P ACKNOWLEDGE FROM SLAVE
START
R/W
STOP
Figure 23. IC Master Reads Slave Immediately After First Byte (Read Mode)
ACKNOWLEDGE FROM SLAVE MSB S SLAVE ADDRESS 1 A DATA A ACKNOWLEDGE FROM MASTER MSB DATA 1 P NO ACKNOWLEDGE FROM MASTER
START
R/W
n BYTES
STOP
Figure 24. IC Master Reads After Setting Slave Register Address (Write Address, Read Data)
ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE
S
SLAVE ADDRESS
0
A
X
WORD ADDRESS
A
P
START
R/W
STOP
ACKNOWLEDGE FROM SLAVE MSB S SLAVE ADDRESS 1 A DATA
ACKNOWLEDGE FROM MASTER MSB A DATA
NO ACKNOWLEDGE FROM MASTER
1
P
START
R/W
STOP
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SERIAL PERIPHERAL INTERFACE (Cont'd) 4.3.2 S-BUS/I2C BUS Timing Diagrams The clock of the S-BUS/I2C BUS of the ST638x SPI (single master only) has a fixed bus clock frequency of 62.5KHz. All the devices connected to the bus must be able to follow transfers with freFigure 25. S-BUS Timing Diagram
SCL 0 1 1 2 3
quencies up to 62.5KHz, either by being able to transmit or receive at that speed or by applying the clock synchronization procedure which will force the master into a wait state and stretch low periods.
4
5
6
7
A
SEN (TRANSMIT)
SDA (TRANSMIT)
^^^ SDA pulled low by receiver if acknowledged.
SEN (RECEIVE)
SDA (RECEIVE)
^^^ SDA pulled low by SPI Peripheral.
SCL 0 1 1 2 3 4 5 6 7 A
SEN (START)
SDA (START)
^^^ SDA pulled low by receiver if acknowledged.
SCL 0 1 1 2 3 4 5 6 7 A
SEN (STOP)
SDA (STOP) SDA pulled low by receiver if acknowledge. If in receive then there will be no ACK. by the SPI.
^^^
VA00454
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 26. I2C BUS Timing Diagram
SCL
0 1 2 3 4 5 6 7 A
SDA (TRANSMIT) SDA pulled low by receiver if acknowledged.
SDA (RECEIVE) SDA pulled low by SPI Peripheral.
SCL
0 1 2 3 5 6 7 A
SDA (START) SDA pulled low by receiver if acknowledged.
SCL
0 1 2 3 4 5 6 7 A
SDA (STOP) SDA pulled low by receiver if acknowledge. If in receive then there will be no ACK. by the SPI.
VA00455
Note: The third pin, SEN, should be high; it is not used in the I2C BUS. Logically SDA is the AND of the S-BUS SDA and SEN.)
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SERIAL PERIPHERAL INTERFACE (Cont'd) 4.3.3 Compatibility S-BUS/I2C BUS Using the S-BUS protocol it is possible to implement mixed system including S-BUS/I2C BUS bus peripherals. In order to have the compatibility with the I2C BUS peripherals, the devices including the S-BUS interface must have their SDA and SEN pins connected together as shown in the following Figure 27. S-BUS/ I2C BUS Mixed Configurations
Figure 27 (a and b). It is also possible to use mixed S-BUS/I2C BUS protocols as showed in Figure 27 (c). S-BUS peripherals will only react to S-BUS protocol signals, while I2C BUS peripherals will only react to I2C BUS signals. Multimaster configuration is not possible with the ST63xx SPI (single master only).
SCL SDA SEN
SCL SDA SEN
SCL SDA SEN
SCL SDA SEN
ST6 S-BUS PROTOCOL SCL SDA I2C-BUS SLAVE
ST6 I2C-BUS PROTOCOL SCL SDA I2C-BUS SLAVE
VA00457
a
VA00456
b
SCL SDA SEN ST6 S-BUS/I2C-BUS PROTOCOL
SCL SDA SEN
SCL SDA I2C-BUS SLAVE
VA00452
c
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SERIAL PERIPHERAL INTERFACE (Cont'd) 4.3.4 STD SPI Protocol (Shift Register) This protocol is similar to the I2C BUS with the exception that there is no acknowledge pulse and there are no stop or start bits. The clock cannot be slowed down by the external peripherals. In this case all three outputs should be high in order not to lock the software I/Os from functioning. SPI Standard Bus Protocol: The standard bus protocol is selected by loading the SPI Control Regis-
ter 1 (SCR1 Add. EBh). Bit 0 named I2C must be set at one and bit 1 named STD must be reset. When the standard bus protocol is selected bit 2 of the SCR1 is meaningless. This bit named STOP bit is used only in I2C BUS or SBUS. However take care that THE STOP BIT MUST BE RESET WHEN THE STANDARD PROTOCOL IS USED. This bit is set to ZERO after RESET.
Figure 28. Software Bus (Hardware Bus Disabled) Timing Diagram
CLOCK (was SCL) 0 1 2 3 4 5 6 7
IDENT (was SEN, this is optionally controlled by software; output as far as hardware is concerned is high).
DATA (was SDA, TRANSMIT)
DATA (was SDA, RECEIVE)
VA00453
4.3.5 SPI Data/Control Register For I/O details on SCL (Serial Clock), SDA (Serial Data) and SEN (Serial Enable) please refer to I/O Ports description with reference to the following registers: Port C data register, Address C2h (Read/Write). - BIT D0 "SCL" - BIT D1 "SDA" - BIT D3 "SEN" Port C data direction register, Address C6h (Read/ Write).
SPI Serial Data Register (SSDR) Address: CCh - Read/Write Reset Value: XXh
7 0
SSDR SSDR SSDR SSDR SSDR SSDR SSDR SSDR 7 6 5 4 3 2 1 0
SSDR7-0. These are the SPI data bits. They can be neither read nor written when SPI is operating (BUSY bit set). They are undefined after reset.
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SERIAL PERIPHERAL INTERFACE (Cont'd) SPI Control Register 1 (SCR1) Address: EBh - Write only Reset Value: 00h
7 STR STP STD/ SPI 0 S-BUS/ 2 I CBUS
SPI Control Register 2 (SCR2) Address: ECh - Read/Write Reset Value: 00h
7 TX/RX VRY/S ACN 0 BSY
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. b7-b4. These bits are not used. STR. This is Start bit for I2C BUS/S-BUS. This bit is meaningless when STD/SPI enable bit is cleared to zero. If this bit is set to one and STD/SPI bit is also set to "1" then SPI Start generation, before beginning of transmission, is enabled. Set to zero after reset. STP. This is Stop bit for I2C BUS/S-BUS. This bit is meaningless when STD/SPI enable bit is cleared to zero. If this bit is set to one and STD/SPI bit is also set to "1" then SPI Stop condition generation is enabled. STP bit must be reset when standard protocol is used (this is also the default reset conditions). Set to zero after reset. STD, SPI Enable. This bit, in conjunction with SBUS/I2C BUS bit, allows the SPI disable and will select between I2C BUS/S-BUS and Standard shift register protocols. If this bit is set to one, it selects both I2C BUS and S-BUS protocols; final selection between them is made by S-BUS/I2C BUS bit. If this bit is cleared to zero when S-BUS/I2C BUS is set to "1" the Standard shift register protocol is selected. If this bit is cleared to "0" when SBUS/I2C BUS is cleared to 0 the SPI is disabled. Set to zero after reset. S-BUS/I2C BUS Selection. This bit, in conjunction with STD/SPI bit, allows the SPI disable and will select between I2C BUS and S-BUS protocols. If this bit is cleared to "0" when STD bit is also "0", the SPI interface is disabled. If this bit is cleared to zero when STD bit is set to "1", the I2C BUS protocol will be selected. If this bit is set to "1" when STD bit is set to "1", the S-BUS protocol will be selected. Cleared to zero after reset. Table 12. SPI Mode Selection
D1 STD/SP 0 0 1 1 D0 S-BUS/I2C BUS 0 1 0 1 SPI Function Disabled STD Shift Reg. I2C BUS S-BUS
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. b7-b4. These bits are not used. TX/RX. Write Only. When this bit is set, current byte operation is a transmission. When it is reset, current operation is a reception. Set to zero after reset. VRY/S. Read Only/Write Only. This bit has two different functions in relation to read or write operation. Reading Operation: when STD and/or TRX bits is cleared to 0, this bit is meaningless. When bits STD and TX are set to 1, this bit is set each time BSY bit is set. This bit is reset during byte operation if real data on SDA line are different from the output from the shift register. Set to zero after reset. Writing Operation: it enables (if set to one) or disables (if cleared to zero) the interrupt coming from VSYNC pin. Undefined after reset. Refer to OSD description for additional information. ACN. Read Only. If STD bit (D1 of SCR1 register) is cleared to zero this bit is meaningless. When STD is set to one, this bit is set to one if no Acknowledge has been received. In this case it is automatically reset when BSY is set again. Set to zero after reset. BSY. Read/Set Only. This is the busy bit. When a one is loaded into this bit the SPI interface start the transmission of the data byte loaded into SSDR data register or receiving and building the receive data into the SSDR data register. This is done in accordance with the protocol, direction and start/ stop condition(s). This bit is automatically cleared at the end of the current byte operation. Cleared to zero after reset. Note: The SPI shift register is also the data transmission register and the data received register; this feature is made possible by using the serial structure of the ST638x and thus reducing size and complexity.
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SERIAL PERIPHERAL INTERFACE (Cont'd) During transmission or reception of data, all access to serial data register is therefore disabled. The reception or transmission of data is started by setting the BUSY bit to "1"; this will be automatically reset at the end of the operation. After reset, the busy bit is cleared to "0", and the hardware SPI disabled by clearing bit 0 and bit 1 of SPI control register 1 to "0". The outputs from the hardware SPI are "ANDed" to the standard I/O software controlled outputs. If the hardware SPI is in operation the Port C pins related to the SPI should be configured as outputs using the Data Direction Register and should be set high. When the SPI is configured as the S-BUS, the three pins PC0, PC1 and PC3 become the pins SCL, SDA and SEN respectively. When configured as the I2C BUS the pins PC0 and PC1 are configured as the pins SCL and SDA; PC3 is not driven and can be used as a general purpose I/O pin. In the case of the STD SPI the pins PC0 and PC1 become the signals CLOCK and DATA, PC3 is not driven and can be used as
general purpose I/O pin. The VERIFY bit is available when the SPI is configured as either S-BUS or I2C BUS. At the start of a byte transmission, the verify bit is set to one. If at any time during the transmission of the following eight bits, the data on the SDA line does not match the data forced by the SPI (while SCL is high), then the VERIFY bit is reset. The verify is available only during transmission for the S-BUS and I2C BUS; for other protocol it is not defined. The SDA and SCL signal entering the SPI are buffered in order to remove any minor glitches. When STD bit is set to one (S-BUS or I2C BUS selected), and TRX bit is reset (receiving data), and STOP bit is set (last byte of current communication), the SPI interface does not generate the Acknowledge, according to S-BUS/I2C BUS specifications. PCO-SCL, PC1-SDA and PC3SEN lines are standard drive I/O port pins with open-drain output configuration (maximum voltage that can be applied to these pins is VDD+ 0.3V).
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4.4 14-BIT VOLTAGE SYNTHESIS TUNING PERIPHERAL The ST638x on-chip voltage synthesis tuning peripheral has been integrated to allow the generation of tuning reference voltage in low/mid end TV set applications. The peripheral is composed of a 14-bit counter that allows the conversion of the digital content in a tuning voltage, available at the VS output pin, by using Pulse Width Modification (PWM), and Bit Rate Multiplier (BRM) techniques. The 14-bit counter gives 16384 steps which allows a resolution of approximately 2mV over a tuning voltage of 32V; this corresponds to a tuning resolution of about 40KHz per step in the UHF band (the actual value will depend on the characteristics of the tuner). The tuning word consists of a 14-bit word contained in the registers VSDATA1 (location 0EEh) and VSDATA2 (location 0EFh). Coarse tuning (PWM) is performed using the seven MSBits, while fine tuning (BRM) is performed using the data in the seven LSBits. With all zeros loaded the output is zero; as the tuning voltage increases from all zeros, the number of pulses in one period increase to 128 with all pulses being the same width. For values larger than 128, the PWM takes over and the number of pulses in one period remains constant at 128, but the width changes. At the other end of the scale, when almost all ones are loaded, the pulses will start to link together and the number of pulses will decrease. When all ones are loaded, the output will be almost 100% high but will have a low pulse (1/16384 of the high pulse). 4.4.1 Output Details Inside the on-chip Voltage Synthesis are included the register latches, a reference counter, PWM and BRM control circuitry. In the ST638x the clock for the 14-bit reference counter is 2MHz derived from the 8MHz system clock. From the circuit point of view, the seven most significant bits control the coarse tuning, while the seven least significant bits control the fine tuning. From the application and software point of view, the 14 bits can be considered as one binary number. As already mentioned the coarse tuning consists of a PWM signal with 128 steps; we can consider the fine tuning to cover 128 coarse tuning cycles. The addition of pulses is described in the following Table. Table 13. . Fine Tuning Pulse Addition
Fine Tuning (7 LSB) 0000001 0000010 0000100 0001000 0010000 0100000 1000000 N of pulses added at the following cycles (0... 127) 64 32, 96 16, 48, 80, 112 8, 24,....104, 120 4, 12,....116, 124 2, 6,.....122, 126 1, 3,.....125, 127
The VS output pin has a standard drive push-pull output configuration. 4.4.2 VS Tuning Cell Registers Voltage Synthesis Data Register 1 (VSDR1) Address: EEh - Write only Reset Value: XXh
7 0
VSDR1 VSDR1 VSDR1 VSDR1 VSDR1 VSDR1 VSDR1 VSDR1 7 6 5 4 3 2 1 0
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7-D0. These are the 8 least significant VS data bits. Bit 0 is the LSB. This register is undefined on reset. Voltage Synthesis Data Register 2 (VSDR2) Address: EFh - Write only Reset Value: XXh
7 0 VSDR2 VSDR2 VSDR2 VSDR2 VSDR2 VSDR2 5 4 3 2 1 0
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7-D6. These bits are not used. D5-D0. These are the 6 most significant VS data bits. Bit 5 is the MSB. This register is undefined on reset.
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4.5 6-BIT PWM D/A CONVERTERS The D/A macrocell contains up to six PWM D/A outputs (31.25kHz repetition, DA0-DA5) with six bit resolution. Each D/A converter of ST638x is composed by the following main blocks: - pre-divider - 6-bit counter - data latches and compare circuits The pre-divider uses the clock input frequency (8MHz typical) and its output clocks the 6-bit freerunning counter. The data latched in the six registers (E0h, E1h, E2h, E3h, E6h and E7h) control the six D/A outputs (DA0,1,2, 3, 4 and 5). When all zeros are loaded the relevant output is an high logic level; all 1's correspond to a pulse with a 1/64 duty cycle and almost 100% zero level. The repetition frequency is 31.25kHz and is related to the 8MHz clock frequency. Use of a different oscillator frequency will result in a different repetition frequency. All D/A outputs are open-drain with standard current drive capability and able to withstand up to 12V. DA0-DA5 Data/Control Register (DADCR) Address: E0h, E1h, E2h, E3h, E4h, E5h, E6h, E7h, - Write only Reset Value: XXh
7 0 DADCR DADCR DADCR DADCR DADCR DADCR 5 4 3 2 1 0
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. DADCR0-DADCR5. These are the 6 bits of the PWM digital to analog converter. Undefined after reset. Figure 29. 6-bit PWM D/A Output Configuration
DA0-DA5 OUT (OPEN-DRAIN, 12V) Out
N
VA00343
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4.6 AFC A/D COMPARATOR The AFC macrocell contains an A/D comparator with five levels at intervals of 1V from 1V to 5V. The levels can all be lowered by 0.5V to effectively double the resolution. 4.6.1 A/D Comparator The A/D used to perform the AFC function (when high threshold is selected) has the following voltage levels: 1,2,3,4 and 5V. Bits 0-2 of AFC result register (E4h address) will provide the result in binary form (less than 1V is 000, greater than 5V is 101). If the application requires a greater resolution, the sensitivity can be doubled by clearing to zero bit 2 of the OUTPUTS control register, address E5h. In this case all levels are shifted lower by 0.5V. If the two results are now added within a software routine then the A/D S-curve can be located within a resolution of 0.5V. The A/D input has high impedance able to withstand up to 13V signals (input level tolerances 200mV absolute and 100mV relative to 5V). Figure 30. AFC Input Configuration
AFC (INPUT, HIGH IMPEDANCE)
AFC, IR and OSD Result Register (AFCR) Address: E4h - Read only Reset Value: 00h
7 VSYNC IR AD2 AD1 0 AD0
D7-D5. These bits are not used. VSYNC. This bit reads the status of the VSYNC pin. It is inverted with respect to the pin. IR. This bit reads the status of the IR latch. If a signal has been latched this bit will be high. AD2-AD0. These bits store the real time conversion of the value present on the AFC input pin. Undefined reset value. AFC Shift Register (AFSR) Address: E4h - Write only Reset Value: 00h
7 ADSR3 0 -
In
A AFC
VA00458
D7, D6, D5, D4, D3, D1, D0. These bits are not used. ADCR3. This bit determines the voltage range of the AFC input. Writing a zero will select the 0.5V to 4.5V range. Writing a one will select the 1.0V to 5.0V range. Undefined after reset. Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used.
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4.7 DEDICATED LATCHES Two latches are available which may generate interrupts to the ST638x core. The IR latch is set either by the falling or rising edge of the signal on pin PC6(IRIN). If bit 1 (IRPOSEDGE) of the latches register (E9h) is high, then the latch will be triggered on the rising edge of the signal at PC6(IRIN). If bit 1 (IRPOSEDGE) is low, then the latch will be triggered on the falling edge of the signal at PC6(IRIN). The IR latch can be reset by setting bit 3 (RESIRLAT) of the latches register; the bit is write only and a high should be written every time the IR latch needs to be reset. If bit 2 (IRINTEN) of the latches register (E9h) is high, then the output of the IR latch, IRINTN, may generate an interrupt (#0). IRINTN is inverted with respect to the state of the IR latch. If bit 2 (IRINTEN) is low, then the output of the IR latch, IRINTN, is forced high.The state of the IR latch may be read from bit 3 (IRLATCH) of register E4h; if the IR latch is set, then bit 3 will be high. The PWR latch is set either by the falling or rising edge of the signal on pin PC4(PWRIN). If bit 4 (PWREDGE) of the latches register (E9h) is high, then the latch will be triggered on the rising edge of the signal at PC4(PWRIN). If bit 4 (PWREDGE) is low, then the latch will be triggered on the falling edge of the signal at PC4(PWRIN). The PWR latch can be reset by setting bit 6 (RESPWRLAT) of the latches register; the bit is set only and a high should be written every time the PWR latch needs to be reset. If bit 5 (PWRINTEN) of the latches register (E9h) is high, then the output of the PWR latch, PWRINTN, may generate an interrupt (#4). PWRINTN is inverted with respect to the state of the PWR latch. If bit 5 (PWRINTEN) is low, then the output of the PWR latch, PWRINTN, is forced high. Dedicated Latches Control Register (DLCR) Address: E9h - Write only Reset Value: XXh
7 IRRESP- PWRINT- PWRED RESIR- IRINTPOSED WRLAT EN GE LAT EN GE 0 -
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7. This bit is not used RESPWRLAT. Resets the PWR latch; this bit is write only. PWRINTEN. This bit enables the PWRINT signal (#4) from the latch to the ST638x core. Undefined after reset. PWREDGE. The bit determines the edge which will cause the PWRIN latch to be set. If this bit is high, than the PWRIN latch will be set on the rising edge of the PWRIN signal. Undefined after reset. RESIRLAT. Resets the IR latch; this bit is write only. Undefined after Reset. IRINTEN. This bit enables the IRINTN signal (#0) from the latch to the ST638x core. Undefined after reset. IRPOSEDGE. The bit determines the edge which will cause the IR latch to be set. If this bit is high, than the IR latch will be set on the rising edge of the IR signal. Undefined after reset. D0. This bit is not used
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4.8 ON-SCREEN DISPLAY (OSD) The ST638x OSD macrocell is a CMOS LSI character generator which enable display of characters and symbols on the TV screen. The character rounding function enhances the readability of the characters. The ST638x OSD receives horizontal and vertical synchronization signal and outputs screen information via R, G, B and blanking pins. The main characteristics of the macrocell are listed below - Number of display characters: 5 lines by 15 columns. - Number of character types: 128 characters in two banks of 64 characters. Only one bank per screen can be used. - Character size: Four character heights (18H, 36H, 54H, 72H), two heights are available per screen, programmable by line. - Character format: 6 x 9 dots with character rounding function. - Character colour: Eight colours available programmable by word. - Display position: 64 horizontal positions by 2/ fOSC and 63 vertical positions by 4H - Word spacing: 64 positions programmable from 2/fOSC to 128/fOSC. - Line spacing: 63 positions programmable from 4 to 252 H. - Background: No background, square background or fringe background programmable by word. - Background colour: Two of eight colours available programmable by word. - Display output: Three character data output terminals (R,G,B) and a blank output terminal. - Display on/off: Display data may be programmed on or off by word or entire screen. The entire screen may be blanked. 4.8.1 Format Specification The entire display can be turned on or off through the use of the global enable bit or the display may be selectively turned on or off by word. To turn off the entire display, the global enable bit (GE) should be zero. If the global enable is one, the display is controlled by the word enable bits (WE). The global enable bit is located in the global enable register. The word enable bit is located in the space character preceding the word. Each line must begin with a format character which describes the format of that line and of the first word. This character is not displayed. A space character defines the format of subsequent words. A space character is denoted by a one in bit 6 in the display RAM. If bit 6 of the display RAM is a zero, the other six bits define one of the 64 display characters. The colour, background and enable can be programmed by word. This information is encoded in the space character between words or in the format character at the beginning of each line. Five bits define the colour and background of the following word, and determine whether it will be displayed or not. Characters are stored in a 6 x 9 dot format. One dot is defined vertically as 2H (horizontal lines) and horizontally as 2/fOSC if the smallest character size is enabled. There is no space between characters or lines if the vertical space enable (VSE) and horizontal space enable (HSE) bits are both zero. This allows the use of special graphics characters. The normal alphanumeric character set is formatted to be 5 x 7 with one empty row at the top and one at the bottom and one empty column at the right. If VSE and HSE are both zero, then the spacing between alphanumeric characters is 1 dot and the spacing between lines of alphanumeric characters is 2H. The character size is programmed by line through the use of the size bit (S) in the format character and the global size bits (GS1 and GS2). The vertical spacing enable bit (VSE) located in the format character controls the spacing between lines. If this bit is set to one, the spacing between lines is defined by the vertical spacing register, otherwise the spacing between lines is 0. The spacing between words is controlled by the horizontal space enable bit (HSE) located in the space character. If this bit is set to one, the spacing between words is defined by the horizontal spacing register, otherwise the space character width of 6 dots is the spacing between words. The formats for the display character, space character and format character are described hereafter.
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ON-SCREEN DISPLAY (Cont'd) Space Character Register (SCR) See Data RAM table description for Specific Address - Write only
7 "1" R G B BGS WE 0 HSE
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7. Not used. D6. This pin is fixed to "1". R, G, B. Colour. The 3 colour control bits define the foreground colour of the following word as shown in table below. Table 14. Space Character Register Colour Setting
R 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 Colour Black Blue Green Cyan Red Magenta Yellow White
space between alphanumeric characters will be one dot. "0" - The space between words is equal to the width of the space character, which is 6 dots. "1" - The space between words is defined by the value in the horizontal space register plus the width of the space character. Format Character Register (FCR) See Data RAM table description for Specific Address - Write only
7 S R G B BGS WE 0 VSE
BGS. Background Select. The background select bit selects the desired background colour for the following word. There are two possible backgrounds defined by the bits in the Background Control Register. "0" - The background on the following word is enabled by BG0 and the colour is set by R0, G0, and B0. "1" -The background on the following word is enabled by BG1 and the colour is set by R1, G1, and B1. WE. Word Enable. The word enable bit defines whether or not the following word is displayed. "0" - The word is not displayed. "1" -If the global enable bit is one, then the word is displayed. HSE. Horizontal Space Enable. The horizontal space enable bit determines the spacing between words. The space between characters is always 0. The alphanumeric character set is implemented in a 5 x 7 format with one empty column to the right and one empty row above and below so that the
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7. This bit is not used S. Character Size. The character size bit, along with the global size bits (GS2 and GS1) located in the horizontal space register, specify the character size for each line as defined in Table 16. R, G, B. Colour. The 3 colour control bits define the foreground colour of the following word as shown in Table 15. BGS. Background Select. The background select bit selects the desired background for the following word. There are two possible backgrounds defined by the bits in the Background Control Register. "0" - The background on the following word is enabled by BG0 and the colour is set by R0, G0, and B0. "1" - The background on the following word is enabled by BG1 and the colour is set by R1, G1, and B1. WE. Word Enable. The word enable bit defines whether or not the following word is displayed. "0" - The word is not displayed. "1" - If the global enable bit is one, then the word is displayed. VSE. Vertical Space Enable. The vertical space enable bit determines the spacing between lines. "0" - The space between lines is equal to 0H. The alphanumeric character set is implemented in a 5 x 7 format with one empty column to the right and one empty row above and one below and stored in a 6 x 9 format. "1" - The space between lines is defined by the value in the vertical space register.
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ON-SCREEN DISPLAY (Cont'd) Table 15. Format Character Register Colour Setting.
R 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 Colour Black Blue Green Cyan Red Magenta Yellow White
Table 16. Format Character Register Size
GS2 0 0 0 0 1 1 1 1 GS1 0 0 1 1 0 0 1 1 S 0 1 0 1 0 1 0 1 Vertical Height 18H 36H 18H 54H 36H 54H 36H 72H Horizontal length 6 TDOT 12 TDOT 6 TDOT 18 TDOT 12 TDOT 18 TDOT 12 TDOT 24 TDOT
Character Types The character set is user defined as ROM mask option. Register and RAM Addressing The OSD contains seven registers and 80 RAM locations. The seven registers are the Vertical Start Address register, Horizontal Start Address register, Vertical Space register, Horizontal Space register, Background Control register, Global Enable register and Character Bank Select register. The Global Enable register can be written at any time by the ST63 Core. The other six registers and the RAM can only be read or written to if the global enable is zero. The six registers and the RAM are located on two pages of the paged memory of the ST638x MCUs; the Character Bank Select register is located outside the paged memory at address EDh. Each page contains 64 memory locations. This paged memory is at memory locations 00h to 3Fh in the ST638x memory map. A page of memory is enabled by setting the desired page bit, located in the Data Ram Bank Register, to a one. The page register is location E8h. A one in bit five selects page 5, located on the OSD and a one in bit 6 selects page 6 on the OSD. Table 17 shows the addresses of the OSD registers and RAM. Table 17. OSD Control Registers and Data RAM Addressing
Page Address 5 00h - 3Fh 6 00h - 0Fh 6 10h 6 11h 6 12h 6 13h 6 14h 6 17h No Page EDh Register or RAM RAM Locations 00h - 3Fh RAM Locations 00h - 0Fh Vertical Start Register Horizontal Start Register Vertical Space Register Horizontal Space Register Background Control Register Global Enable Register Character Bank Select Register
Display Character Register (DCR) See Data RAM table description for Specific Address - Write only
7 "0" C5 C4 C3 C2 C1 0 C0
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7. This bit is not used. D6. This bit is fixed to "0". C5-C0. Character type. The 6 character type bits define one of the 64 available character types. These character types are shown on the following pages.
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ON-SCREEN DISPLAY (Cont'd) OSD Global Enable Register (OGER) Address: 17h, Page 6 - Write only
7 0 GE
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. This register contains the global enable bit (GE). It is the only register that can be written at any time regardless of the state of the GE bit. It is a write only register. Vertical Start Address Register (VSAR) Address: 10h, Page 6 - Write only
7 FR VSA5 VSA4 VSA3 VSA2 VSA1 0 VSA0
start positions of interval 4H. The first start position will be the fourth line of the display. The vertical start address is defined VSA0 by the following formula. Vertical Start Address = 4H(25(VSA5) + 24(VSA4) + 23(VSA3) + 22(VSA2) + 21(VSA1) + 20(VSA0)) The case of all Vertical Start Address bits being zero is illegal. Horizontal Start Address Register (HSAR) Address: 11h, Page 6 - Write only
7 SBD HSA5 HSA4 HSA3 HSA2 HSA1 0 HSA0
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7-D1. These bits are not used GE. Global Enable. This bit allows the entire display to be turned off. "0" - The entire display is disabled. The RAM and other registers of the OSD can be accessed by the Core. "1" - Display of words is controlled by the word enable bits (WE) located in the format or space character. The other registers and RAM cannot be accessed by the Core. D7. This bit is not used FR. Fringe Background. This bit changes the background from a box background to a fringe background. The background is enabled by word as defined by either BG0 or BG1. "0" - The background is defined to be a box which is 7 x 9 dots. "1" - The background is defined to be a fringe. VSA5-VSA0. Vertical Start Address. These bits determine the start position of the first line in the vertical direction. The 6 bits can specify 63 display
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7. This bit is not used. SBD. Space Blanking Disable. This bit controls whether or not the background is displayed when outputing spaces. If two background colours are used on adjacent words, then the background should not be displayed on spaces in order to make a nice break between colours. If an even background around an area of text is desired, as in a menu, then the background should be displayed when outputing spaces. "0" - The background during spaces is controlled by the background enable bits (BG0 and BG1) located in the Background Control register. "1" - The background is not displayed when outputing spaces. HSA5, HSA0 - Horizontal Start Address bits. These bits determine the start position of the first character in the horizontal direction. The 6 bits can specify 64 display start positions of interval 2/fOSC or 400ns. The first start position will be at 4.0ms because of the time needed to access RAM and ROM before the first character can be displayed. The horizontal start address is defined by the following formula. Horizontal Start Address = 2/fOSC(10.0 + 25(HSA5) + 24(HSA4) + 23(HSA3) + 22(HSA2) + 21(HSA1) + 20(HSA0))
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ON-SCREEN DISPLAY (Cont'd) Vertical Space Register (VSR) Address: 12h, Page 6 - Write only Reset Value: XXh
7 SCB VS5 VS4 VS3 VS2 VS1 0 VS0
Horizontal Space Register (HSR) Address: 13h, Page 6 - Write only Reset Value: XXh
7 GS2 GS1 HS5 HS4 HS3 HS2 HS1 0 HS0
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7. This bit is not used SCB. Screen Blanking. This bit allows the entire screen to be blanked. "0" - The blanking output signal (VBLK) is active only when displaying characters. "1" - The blanking output signal (VBLK) is always active. Characters in the display RAM are still displayed. When this bit is set to one, the screen is blanked also without setting the Global Enable bit to one (OSD disabled). VS5, VS0. Vertical Space. These bits determine the spacing between lines if the Vertical Space Enable bit (VSE) in the format character is one. If VSE is zero there will be no spaces between lines. The Vertical Space bits can specify one of 63 spacing values from 4H to 252H. The space between lines is defined by the following formula. Space between lines = 4H(25(VS5) + 24(VS4) + 23(VS3) + 22(VS2) + 21(VS1) + 20(VS0)) The case of all Vertical Start Address bits being zero is illegal.
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. GS2,GS1. Global Size. These bits along with the size bit (S) located in the Character format word specify the character size for each line as defined in Table 18. Table 18. Horizontal Setting
GS2 GS1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 S 0 1 0 1 0 1 0 1
Space
Register
Size
Vertical Height 18H 36H 18H 54H 36H 54H 36H 72H
Horizontal Length 6 TDOT 12 TDOT 6 TDOT 18 TDOT 12 TDOT 18 TDOT 12 TDOT 24 TDOT
Note: TDOT=2/fOSC HS5, HS0. Horizontal Space. These bits determine the spacing between words if the Horizontal Space Enable bit (HSE) located in the space character is a one. The space between words is then equal to the width of the space character plus the number of dots specified by the Horizontal Space bits. The 6 bits can specify one of 64 spacing values ranging from 2/fOSC to 128/fOSC. The formula is shown below for the smallest size character(18H). If larger size characters are being displayed the spacing between words will increase proportionately. Multiply the value below by 2, 3 or 4 for character sizes of 36H, 54H and 72H respectively. Space between words (not including the space character)=2/fOSC(1+25(HS5)+24(HS4)+23(HS3) +22(HS2)+ 21(HS1)+20(HS0))
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ON-SCREEN DISPLAY (Cont'd) Background Control Register (BCR) Address 14h, Page 6 - Write only
7 R1 R0 G1 G0 B1 B0 BK1 0 BK0
Table 19. Background Register Colour Setting
RX 0 0 0 0 1 1 1 1 GX 0 0 1 1 0 0 1 1 BX 0 1 0 1 0 1 0 1 Colour Black Blue Green Cyan Red Magenta Yellow White
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. This register sets up two possible backgrounds. The background select bit (BGS) in the format or space character will determine which background is selected for the current word. R1,R0,G1,G0,B1,B0. Background Colour.These bits define the colour of the specified background, either background 1 or background 0 as defined in table below. BK1,BK0. Background Enable.These bits determine if the specified background is enabled or not. "0" - The following word does not have a background. "1" - There is a background around the following word.
Character Bank Select Register (CBSR) Address EDh, No Page - Write only Reset Value: XXh
7 0 BS
Caution: This register contains at least one write only bit. Single bit instructions (SET, RES, INC and DEC) should not be used. D7-D1. These bits are not used BS. Bank Select. This bit select the character bank to be used. The lower bank is selected with 0. The value can be modified only when the OSD is OFF (GE=0). No reset value.
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ON-SCREEN DISPLAY (Cont'd) OSD Data RAM The contents of the data RAM can be accessed by the ST638x MCUs only when the global enable bit (GE) in the Global Enable register is a zero. The first character in every line is the format character. This character is not displayed. It defines the size of the characters in the line and contains the vertical space enable bit. This character also defines the colour, background and display enable for the first word in the line. Subsequent characTable 20. OSD RAM Map
Column A0 A1 A2 A3 Page 5 5 5 5 6 0 0 0 0 0 A5 0 0 1 1 0 A4 LINE 0 1 1 2 0 3 1 4 0 5 FT FT FT FT FT 1 1 0 0 0 Ch Ch Ch Ch Ch 2 0 1 0 0 Ch Ch Ch Ch Ch 3 1 1 0 0 Ch Ch Ch Ch Ch 4 0 0 1 0 Ch Ch Ch Ch Ch 5 1 0 1 0 Ch Ch Ch Ch Ch
ters are either spaces or one of the 64 available character types. The space character defines the colour, background, display enable and horizontal space enable for the following word. Since there are 5 display lines of 15 characters each, the display RAM must contain 5 lines x (15 characters + 1 format character) or 80 locations. The RAM size is 80 locations x 7 bits. The data RAM Map is shown in Table 20.
6 0 1 1 0
7 1 1 1 1
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1 Ch Ch Ch Ch Ch
13 1 0 1 1 Ch Ch Ch Ch Ch
14 0 1 1 1 Ch Ch Ch Ch Ch
15 1 1 1 1 Ch Ch Ch Ch Ch
Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch AVAILABLE SCREEN SPACE
Notes: FT. The format character required for each line. Characters in columns 1 through 15 are displayed. Ch. (Byte) Character (Index into OSD character generator) or space character
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ON-SCREEN DISPLAY (Cont'd) Emulator Remarks There are a few differences between emulator and silicon. For noise reasons, the OSD oscillator pins are not available: the internal oscillator cannot be disabled and replaced by an external coil. In the emulator, the Character Bank Select register can be written also with Global Enable bit set, while this is not allowed in the device. Application Notes 1 - The OSD character generator is composed of a dual port video ram and some circuitry. It needs two input signals VSYNC and HSYNC to synchronize its dedicated oscillator to the TV picture. It generates 4 output signals, that can be used from the TV set to generate the characters on the screen. For instance, they can be used to feed the SCART plug, providing an adequate buffer to drive the low impedance (75) of the SCART inputs. 2 - The Core sees the OSD as a number of RAM locations (80) plus a certain number of control registers (6). These 86 locations are mapped in two pages of the dynamic data ram address range (0h.3Fh). In page 5 (load 20h in the register 0E8h), there are 64 bytes of RAM, the ones of the first 4 rows (16 bytes each row, 15 characters per row maximum, plus an hidden leading format character). In page 6 (load 40h in register 0E8h), the 16 bytes of the fifth row (0..0Fh), and the 6 control registers (10h..14h,17h). 3 - The video RAM is a dual port ram. That means that it can be addressed either from the Core or from the OSD circuitry itself. To reduce the complexity of the circuitry, and thus its cost, some restrictions have been introduced in the use of the OSD. a. The Core can Only write to any of the 86 locations (either video RAM or control registers).
b. The Core can Only write to any of the leading 85 locations when the OSD oscillator is OFF. Only the last location (control register 17h in page 6) can be addressed at any time. This is the Global Enable Register, which contains only the GE bit. If it is set, the OSD is on, if it is reset the OSD is off. 4 - The timing of the on/off switching of the OSD oscillator is the following: a. GE bit is set. The OSD oscillator will start on the next VSYNC signal. b. GE bit is reset. The OSD oscillator will be immediately switched off. 5 - To avoid a bad visual impression, it is important that the GE bit is set before the end of the flyback time when changing characters. This can be done inside the VSYNC interrupt routine. The following diagram can explain better: Figure 31. OSD Oscillator ON/OFF Timing
VSYNC BC VV E V
D
A VA00344
time
Notes: A - Picture time: 20 mS in PAL/SECAM. B - VSYNC interrupt, if enabled. C - Starting of OSD oscillator, if GE = 1 D - Flyback time.
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ON-SCREEN DISPLAY (Cont'd) When modifying the picture display (i.e.: a bar graph for an analog control), it is important that the switching on of the GE bit is done before the end of the flyback time (D in Figure 31). If the GE bit is set after the end of the flyback time then the OSD will not start until the beginning of the next frame. This results in one frame being lost and will result in a Flicker on the screen. One method to be sure to avoid the flicker is to wait for the VSYNC interrupt at the start of the flyback; once the VSYNC interrupt is detected, then the GE bit can be set to zero, the characters changed, and the GE set to one. All this should occur before the end of the flyback time in order not to lose a frame. The correct edge of the interrupt must be chosen. The VSYNC pin may alternatively be sampled by software in order to know the status; this can be done by reading bit 4 of register E4h; this bit is inverted with respect to the VSYNC pin. 6 - An OSD end of line Bar is present in the ST638x ROM, EPROM and OTP devices when using the box background mode. The bar appears at the end of the line in the background mode when the last character is a space character, the first format character is defined with
S=0 (size 0)and the box background is not displayed during the space. The bar is the colour of the background defined by the space character. To eliminate the bar: a. If two backgrounds are used then the bar should be moved off the screen by using large word spaces instead of character spaces. If there are not enough spaces before the end of the line, then the location of the valid characters should be moved so they appear at the end of the line (and hence no bar); positioning can be compensated using the horizontal start register. b. If only one background is used, then the other background should be disabled in order to eliminate the bar. 7 - The OSD oscillator external network should consist of a capacitor on each of the OSD oscillator pins to ground together with an inductance between pins. The user should select the two capacitors to be the same value (15pF to 25pF each is recommended). The inductance is chosen to give the desired OSD oscillator frequency for the application (typically 56H).
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ON-SCREEN DISPLAY (Cont'd) Figure 32. Standard OSD Character Set (UP Code)
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5 SOFTWARE
5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction. Furthermore, the program may branch to a selected address depending on the status of any bit of the Data space. The carry bit is stored with the value of the bit when the SET or RES instruction is processed. 5.2 ADDRESSING MODES The ST6 core offers nine addressing modes, which are described in the following paragraphs. Three different address spaces are available: Program space, Data space, and Stack space. Program space contains the instructions which are to be executed, plus the data for immediate mode instructions. Data space contains the Accumulator, the X,Y,V and W registers, peripheral and Input/ Output registers, the RAM locations and Data ROM locations (for storage of tables and constants). Stack space contains six 12-bit RAM cells used to stack the return addresses for subroutines and interrupts. Immediate. In the immediate addressing mode, the operand of the instruction follows the opcode location. As the operand is a ROM byte, the immediate addressing mode is used to access constants which do not change during program execution (e.g., a constant used to initialize a loop counter). Direct. In the direct addressing mode, the address of the byte which is processed by the instruction is stored in the location which follows the opcode. Direct addressing allows the user to directly address the 256 bytes in Data Space memory with a single two-byte instruction. Short Direct. The core can address the four RAM registers X,Y,V,W (locations 80h, 81h, 82h, 83h) in the short-direct addressing mode. In this case, the instruction is only one byte and the selection of the location to be processed is contained in the opcode. Short direct addressing is a subset of the direct addressing mode. (Note that 80h and 81h are also indirect registers). Extended. In the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant bits of the opcode with the byte following the opcode. The instructions (JP, CALL) which use the extended addressing mode are able to branch to any address of the 4K bytes Program space. An extended addressing mode instruction is twobyte long. Program Counter Relative. The relative addressing mode is only used in conditional branch instructions. The instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 locations around the address of the relative instruction. If the condition is not true, the instruction which follows the relative instruction is executed. The relative addressing mode instruction is one-byte long. The opcode is obtained in adding the three most significant bits which characterize the kind of the test, one bit which determines whether the branch is a forward (when it is 0) or backward (when it is 1) branch and the four less significant bits which give the span of the branch (0h to Fh) which must be added or subtracted to the address of the relative instruction to obtain the address of the branch. Bit Direct. In the bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the address of the byte in which the specified bit must be set or cleared. Thus, any bit in the 256 locations of Data space memory can be set or cleared. Bit Test & Branch. The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit test and branch instruction is three-byte long. The bit identification and the tested condition are included in the opcode byte. The address of the byte to be tested follows immediately the opcode in the Program space. The third byte is the jump displacement, which is in the range of -127 to +128. This displacement can be determined using a label, which is converted by the assembler. Indirect. In the indirect addressing mode, the byte processed by the register-indirect instruction is at the address pointed by the content of one of the indirect registers, X or Y (80h,81h). The indirect register is selected by the bit 4 of the opcode. A register indirect instruction is one byte long. Inherent. In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. These instructions are one byte long.
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5.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be divided into six different types: load/store, arithmetic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following paragraphs describe the different types. All the instructions belonging to a given type are presented in individual tables. Table 21. Load & Store Instructions
Instruction LD A, X LD A, Y LD A, V LD A, W LD X, A LD Y, A LD V, A LD W, A LD A, rr LD rr, A LD A, (X) LD A, (Y) LD (X), A LD (Y), A LDI A, #N LDI rr, #N Addressing Mode Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Indirect Indirect Immediate Immediate Bytes 1 1 1 1 1 1 1 1 2 2 1 1 1 1 2 3 Cycles 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Flags Z * C * * * * * * * * * * * * * * * *
Load & Store. These instructions use one, two or three bytes in relation with the addressing mode. One operand is the Accumulator for LOAD and the other operand is obtained from data memory using one of the addressing modes. For Load Immediate one operand can be any of the 256 data space bytes while the other is always immediate data.
Notes: X,Y. Indirect Register Pointers, V & W Short Direct Registers # . Immediate data (stored in ROM memory) rr. Data space register . Affected * . Not Affected
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INSTRUCTION SET (Cont'd) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instructions one operand is always the accumulator while the other can be either a data space memory conTable 22. Arithmetic & Logic Instructions
Instruction ADD A, (X) ADD A, (Y) ADD A, rr ADDI A, #N AND A, (X) AND A, (Y) AND A, rr ANDI A, #N CLR A CLR r COM A CP A, (X) CP A, (Y) CP A, rr CPI A, #N DEC X DEC Y DEC V DEC W DEC A DEC rr DEC (X) DEC (Y) INC X INC Y INC V INC W INC A INC rr INC (X) INC (Y) RLC A SLA A SUB A, (X) SUB A, (Y) SUB A, rr SUBI A, #N Addressing Mode Indirect Indirect Direct Immediate Indirect Indirect Direct Immediate Short Direct Direct Inherent Indirect Indirect Direct Immediate Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Inherent Inherent Indirect Indirect Direct Immediate Bytes 1 1 2 2 1 1 2 2 2 3 1 1 1 2 2 1 1 1 1 2 2 1 1 1 1 1 1 2 2 1 1 1 2 1 1 2 2 Cycles 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Flags Z * C * * * * * * * * * * * * * * * * *
tent or an immediate value in relation with the addressing mode. In CLR, DEC, INC instructions the operand can be any of the 256 data space addresses. In COM, RLC, SLA the operand is always the accumulator.
Notes: X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected # . Immediate data (stored in ROM memory)* . Not Affected rr. Data space register
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INSTRUCTION SET (Cont'd) Conditional Branch. The branch instructions achieve a branch in the program when the selected condition is met. Bit Manipulation Instructions. These instructions can handle any bit in data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations. Table 23. Conditional Branch Instructions
Instruction JRC e JRNC e JRZ e JRNZ e JRR b, rr, ee JRS b, rr, ee Branch If C=1 C=0 Z=1 Z=0 Bit = 0 Bit = 1 Bytes 1 1 1 1 3 3 Cycles 2 2 2 2 5 5 Flags Z * * * * * * C * * * *
Control Instructions. The control instructions control the MCU operations during program execution. Jump and Call. These two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space.
Notes: b. 3-bit address e. 5 bit signed displacement in the range -15 to +16 ee. 8 bit signed displacement in the range -126 to +129
rr. Data space register . Affected. The tested bit is shifted into carry. * . Not Affected
Table 24. Bit Manipulation Instructions
Instruction SET b,rr RES b,rr
Notes: b. 3-bit address; rr. Data space register;
Addressing Mode Bit Direct Bit Direct
Bytes 2 2
Cycles 4 4
* . Not Affected
Flags Z * * C * *
Table 25. Control Instructions
Instruction NOP RET RETI STOP (1) WAIT Addressing Mode Inherent Inherent Inherent Inherent Inherent Bytes 1 1 1 1 1 Cycles 2 2 2 2 2 Flags Z * * * * C * * * *
Notes: 1. This instruction is deactivatedand a WAIT is automatically executed instead of a STOP if the watchdog function is selected. . Affected *. Not Affected
Table 26. Jump & Call Instructions
Instruction CALL abc JP abc
Notes: abc. 12-bit address; * . Not Affected
Addressing Mode Extended Extended
Bytes 2 2
Cycles 4 4
Flags Z * * C * *
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Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 0 0000 JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr RNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 1 0001 CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext CALL abc ext 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 0010 JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 3 0011 JRR b0,rr,ee bt JRS b0,rr,ee bt JRR b4,rr,ee bt JRS b4,rr,ee bt JRR b2,rr,ee bt JRS b2,rr,ee bt JRR b6,rr,ee bt JRS b6,rr,ee bt JRR b1,rr,ee bt JRS b1,rr,ee bt JRR b5,rr,ee bt JRS b5,rr,ee bt JRR b3,rr,ee bt JRS b3,rr,ee bt JRR b7,rr,ee bt JRS b7,rr,ee bt 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 pcr 1 pcr JRZ 4 a,w sd 1 pcr 1 JRZ # 1 LD 2 e prc pcr JRZ 4 w sd 1 2 e prc 1 JRC pcr 1 JRZ # 1 INC 2 e prc 2 JRC 4 pcr JRZ 4 a,v sd 1 2 e prc 1 JRC 4 pcr 1 JRZ # 1 LD 2 e prc 2 JRC 4 pcr JRZ 4 v sd 1 2 e prc 1 JRC 4 pcr 1 JRZ # 1 INC 2 e prc JRC 4 pcr JRZ 4 a,y sd 1 2 e prc 1 JRC # AND a,(x) ind ANDI a,nn imm SUB a,(x) ind SUBI a,nn imm DEC (x) ind # pcr 1 JRZ # 1 LD 2 e prc JRC 4 (x),a ind pcr JRZ 4 y sd 1 2 e prc 1 JRC pcr JRZ 4 a,x pcr 1 JRZ # 1 INC 2 e prc 2 JRC 4 sd 1 2 e prc 1 JRC 4 pcr 1 JRZ # 1 LD 2 e prc 2 JRC 4 pcr JRZ 4 x sd 1 2 e prc 1 JRC 4 4 0100 JRZ # 1 INC 2 e prc 2 JRC 4 5 0101 2 e prc 1 JRC 4 6 0110 JRC 4 a,(x) ind LDI a,nn imm CP a,(x) ind CPI a,nn imm ADD a,(x) ind ADDI a,nn imm INC (x) ind # LD 7 0111 LD LOW HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
Abbreviations for Addressing Modes: dir Direct sd Short Direct imm Immediate inh Inherent ext Extended b.d Bit Direct bt Bit Test pcr Program Counter Relative ind Indirect
Legend: # Indicates Illegal Instructions e 5 Bit Displacement b 3 Bit Address rr 1byte dataspace address nn 1 byte immediate data abc 12 bit address ee 8 bit Displacement
Cycle Operand Bytes Addressing Mode
2 e 1
JRC prc
Mnemonic
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Opcode Map Summary (Continued)
LOW HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 8 1000 JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr RNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr JRNZ e pcr 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 4 abc 2 ext 1 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 ext 1 JP 2 9 1001 JP 2 A 1010 JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr JRNC e pcr 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 B 1011 RES b0,rr b.d SET b0,rr b.d RES b4,rr b.d SET b4,rr b.d RES b2,rr b.d SET b2,rr b.d RES b6,rr b.d SET b6,rr b.d RES b1,rr b.d SET b1,rr b.d RES b5,rr b.d SET b5,rr b.d RES b3,rr b.d SET b3,rr b.d RES b7,rr b.d SET b7,rr b.d 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 2 e 1 pcr 1 pcr 1 JRZ 4 w,a sd 1 inh 1 LD 2 e prc 2 pcr 1 JRZ 2 pcr 1 JRZ 4 w sd 1 WAIT 2 e prc 1 JRC 4 inh 1 DEC 2 e prc 2 JRC 4 pcr 1 JRZ 2 pcr 1 JRZ 4 v,a sd 1 RET 2 e prc 1 JRC 4 pcr 1 JRZ 4 a inh 1 LD 2 e prc 2 JRC 4 pcr JRZ 4 v sd 1 RCL 2 e prc 1 JRC 4 pcr 1 JRZ # 1 DEC 2 e prc 2 JRC 4 pcr 1 JRZ 4 y,a sd 1 2 e prc 1 JRC 4 inh 1 LD 2 e prc 2 JRC 4 pcr 1 JRZ 2 pcr 1 JRZ 4 y sd 1 STOP 2 e prc 1 JRC 4 inh 1 DEC 2 e prc 2 JRC 4 pcr JRZ 4 x,a pcr 1 JRZ 2 sd 1 RETI 2 e prc 1 JRC 4 pcr 1 JRZ 4 pcr 3 JRZ 4 C 1100 JRZ 4 D 1101 LDI 2 rr,nn imm DEC x sd COM a e 1 2 e 1 2 e prc 1 JRC 4 e prc 2 JRC 4 a,rr dir ADD a,(y) ind ADD a,rr dir INC (y) ind INC rr dir LD (y),a ind LD rr,a dir AND a,(y) ind AND a,rr dir SUB a,(y) ind SUB a,rr dir DEC (y) ind DEC rr dir prc 2 JRC 4 a,(y) ind CP prc 1 JRC 4 a,rr dir CP E 1110 JRC 4 a,(y) ind LD F 1111 LD LOW HI 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
1 LD 2
Abbreviations for Addressing Modes: dir Direct sd Short Direct imm Immediate inh Inherent ext Extended b.d Bit Direct bt Bit Test pcr Program Counter Relative ind Indirect
Legend: # Indicates Illegal Instructions e 5 Bit Displacement b 3 Bit Address rr 1byte dataspace address nn 1 byte immediate data abc 12 bit address ee 8 bit Displacement
Cycle Operand Bytes Addressing Mode
2 e 1
JRC prc
Mnemonic
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6 ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, however it is advised to take normal precaution to avoid application of any voltage higher than maximum rated voltages. For proper operation it is recommended that VI and VO must be higher than VSS and smaller than VDD. Reliability is enhanced if unused inputs are connected to an appropriated logic voltage level (VDD or VSS). Power Considerations.The average chip-junction temperature, Tj, in Celsius can be obtained from: Tj= TA + PD x RthJA Where: TA = Ambient Temperature. RthJA =Package thermal resistance (junction-to ambient). PD = Pint + Pport. Pint = IDD x VDD (chip internal power). Pport = Port power dissipation (determined by the user).
Value -0.3 to 7.0 VSS - 0.3 to +13 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to +13 VSS - 0.3 to VDD + 0.3 + 10 + 50 50 150 150 -60 to 150 Unit V V V V V mA mA mA mA C C
Symbol VDD VI VI VO VO IO IO IVDD IVSS Tj TSTG
Parameter Supply Voltage Input Voltage (AFC IN) Input Voltage (Other inputs) Output Voltage (PA4-PA7, PC4-PC7, DA0-DA5) Output Voltage (Other outputs) Current Drain per Pin Excluding VDD, VSS, PA6, PA7 Current Drain per Pin (PA6-PA7) Total Current into VDD (source) Total Current out of VSS (sink) Junction Temperature Storage Temperature
Note: Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
Symbol RthJA Parameter Thermal Resistance Test Conditions PSDIP42 Min. Value Typ. Max. 67 Unit C/W
6.2 RECOMMENDED OPERATING CONDITIONS
Symbol TA VDD fOSC fOSDOSC Parameter Operating Temperature Operating Supply Voltage Oscillator Frequency RUN & WAIT Modes On-screen Display Oscillator Frequency Test Conditions 1 Suffix Versions Min. 0 4.5 Value Typ. 5.0 8 Max. 70 6.0 8.1 8.0 Unit C V MHz MHz
EEPROM INFORMATION The ST63xx EEPROM single poly process has been specially developed to achieve 300.000 Write/Erase cycles and a 10 years data retention.
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6.3 DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C unless otherwise specified). Table 27: DC ELECTRICAL CHARACTERISTICS
Symbol VIL VIH VHYS Parameter Input Low Level Voltage Input High Level Voltage Hysteresis Voltage(1) Test Conditions All I/O Pins All I/O Pins All I/O Pins VDD = 5V DA0-DA5, PB0-PB6, OSD Outputs, PC0-PC7, O0, O1, PA0-PA5 VDD = 4.5V IOL = 1.6mA IOL = 5.0mA PA6-PA7 VDD = 4.5V IOL= 1.6mA IOL= 25mA OSDOSCout OSCout VDD = 4.5V IOL= 0.4mA VS Output VDD = 4.5V IOL= 0.5mA IOL= 1.6mA PB0-PB7, PA0-PA3, OSD Outputs VDD = 4.5V IOH = - 1.6mA OSDOSCout, OSCout, VDD = 4.5V IOH= - 0.4mA VS Output VDD = 4.5V IOH= - 0.5mA PB0-PB6, PA0-PA3, PC0-PC3, VIN= VSS OSCin VIN= VSS OSCin VIN= VSS VIN= VDD OSCin All I/O Input Mode no pull-up OSDOSCin VIN= VDD or VSS Min. 0.8xVDD 1.0 Value Typ. Max. 0.2xVDD Unit V V V
VOL
Low Level Output Voltage
0.4 1.0
V V
VOL
Low Level Output Voltage
0.4 1.0 0.4
V V V
VOL
Low Level Output Voltage
VOL
Low Level Output Voltage
0.4 1.0 4.1
V V V
VOH
High Level Output Voltage
VOH
High Level Output Voltage
4.1
V
VOH
High Level Output Voltage Input Pull Up Current Input Mode with Pull-up Input Pull Up Current Input Leakage Current Input Pull-down current in RESET Input Leakage Current RAM Retention Voltage in RESET Mode Input Leakage Current
4.1
V
IPU IPU IIL IIH IIL IIL IIH VDDRAM IIL IIH
- 100 - 50 - 10 0.1 100
- 50 - 25 -1 1
- 25 - 10 - 0.1 10
A A A A A
-10
10
1.5 Reset Pin with Pull-up VIN= VSS - 50 - 30 - 10
V A
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Table 27: DC ELECTRICAL CHARACTERISTICS
Symbol IIL IIH Parameter Test Conditions AFC Pin VIH= VDD VIL= VSS VIH = 12.0V DA0-DA5, PA4-PA5, PC0-PC7, O0, O1 VOH = VDD DA0-DA5, PA4-PA7, PC4-PC7, O0, O1 VOH = 12V fOSC = 8MHz, ILoad= 0mA VDD= 6.0V fOSC= 8MHz, ILoad= 0mA VDD= 6V fOSC= Not App, ILoad= 0mA VDD= 6V RESET Pin RESET Pin A/D AFC Pin VDD= 5V A/D AFC Pin Relative to other levels VDD= 5V 0.8xVDD 200 100 Min. Value Typ. Max. 1 -1 40 10 A A mA mA mA V V mV mV Unit
Input Leakage Current
A
IOH
Output Leakage Current Output Leakage Current High Voltage Supply Current RUN Mode Supply Current WAIT Mode Supply Current at transition to RESET Reset Trigger Level ON Reset Trigger Level OFF Input Level Absolute Tolerance Input Level Relatice Tolerance(1)
IOH IDD IDD IDD VON VOFF VTA VTR
40 6 3 0.1 16 10 1 0.3xVDD
Note 1. Not 100% Tested
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6.4 AC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C, fOSC=8MHz, VDD=4.5 to 6.0V unless otherwise specified)
Symbol tWRES tOHL tOHL Parameter Minimum Pulse Width High to Low Transition Time High to Low Transition Time Test Conditions RESET Pin PA6, PA7 VDD = 5V, CL = 100pF (2) DA0-DA5, PB0-PB6, OSD Outputs, PC0-PC7 VDD = 5V, CL = 100pF PB0-PB6, PA0-PA3, OSD Outputs, PC0-PC3 VDD = 5V, CL = 100pF Min. 125 Value Typ. Max. Unit ns 100 20 ns ns
tOLH fDA
Low to High Transition Time
20 31.25 62.50 5 >1 million
ns kHz kHz ms cycles years pF pF pF 25 pF
D/A Converter Repetition Frequency (1) SIO Baudrate (1) fSIO tWEE EEPROM Write Time EEPROM WRITE/ERASE CyEndurance cles Retention EEPROM Data Retention (4) CIN Input Capacitance (3) COUT Output Capacitance (3) COSCin, Oscillator Pins Internal (3) COSCout Capacitance COSDin, Oscillator Pins External (3) COSDout Capacitance
TA = 25C One Byte QA LOT Acceptance Criteria TA = 25C All Inputs Pins All Outputs Pins
10
300,000 10
10 10 5
Recommended
15
Notes: 1. A clock other than 8MHz will affect the frequency response of those peripherals (D/A, and SPIs) whose clock is derived from the system clock. 2. The rise and fall times of PORT A have been increased in order to avoid current spikes while maintaining a high drive capability 3. Not 100% Tested 4. Based on extrapolated data
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7 GENERAL INFORMATION
7.1 PACKAGE MECHANICAL DATA Figure 33. 42-Pin Plastic Shrink Dual-In-Line Package
Dim. A
E A2 A1 A L e b2 D b C E1 eA eB E .015 GAGE PLANE LEAD DETAIL eB
mm Min 0.51 3.05 3.81 0.46 1.02 0.23 15.24 1.78 15.24 18.54 1.52 0.000 2.54 3.30 0.25 0.56 1.14 Typ Max 5.08 0.020 Min
inches Typ Max 0.200
A1 A2 b b2 C D E E1 e eA
VR01725G eC
4.57 0.120 0.150 0.180 0.018 0.022 0.040 0.045
0.38 0.009 0.010 0.015 16.00 0.600 0.070 0.600 0.730 0.060 0.630
36.58 36.83 37.08 1.440 1.450 1.460 12.70 13.72 14.48 0.500 0.540 0.570
eB eC L N
3.56 0.100 0.130 0.140 42
Number of Pins
7.2 ORDERING INFORMATION The following chapter deals with the procedure for transfer the Program/Data ROM codes to SGSTHOMSON. Communication of the ROM Codes. To communicate the contents of Program/Data ROM memories to SGS-THOMSON, the customer must send: - one file in INTEL INTELLEC 8/MDS FORMAT for the PROGRAM Memory; - one file in INTEL INTELLEC 8/MDS FORMAT for the EEPROM initial content (this file is optional). - two files in INTEL...FORMAT for the OSD font memory - the option list described below. The program ROM should respect the ROM Memory Map as in Table 4. The ROM code must be generated with an ST6 assembler. Before programming the EPROM, the EPROM programmer buffer must be filled with FFh.
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GENERAL INFORMATION (Cont'd) 7.3 CUSTOMER EEPROM INITIAL CONTENTS: a. The content should be written into an INTEL INTELLEC format file. b In the case of 384 bytes of EEPROM, the starting address is 000h and the end address is 17Fh. The order of the pages (64 bytes each) is an in the specification (i.e. b7, b1 b0: 001, 010, 011, 101, 110. 111). c. Undefined or don't care bytes should have the content FFh. 7.4 OSD Test Character IN ORDER TO ALLOW THE TESTING OF THE ON-CHIP OSD MACROCELL THE FOLLOWING CHARACTER MUST BE PROVIDED AT THE FIXED 3Fh (63) POSITION OF THE SECOND OSD BANK. Listing Generation & Verification. When SGS-THOMSON receives the files, a computer listing is generated from them. This listing refers extractly to the mask that will be used to produce the microcontroller. Then the listing is returned to 7.5 ORDERING INFORMATION TABLE
Sales Type ST6365B1/ XXX ST6367B1/ XXX ST6375B1/ XXX ST6377B1/ XXX ST6385B1/ XXX ST6387B1/ XXX ROM/ EEPROM Size 8K/ 384 Bytes 8K/ 384 Bytes 14K/ 384 Bytes 14K/ 384 Bytes 20K/ 384 Bytes 20K/ 384 Bytes D/ A Converter 4 6 4 6 4 6 Temperature Range 0 to 0 to 0 to 0 to 0 to 0 to + 70 + 70 + 70 + 70 + 70 + 70 C C C C C C Package PSDIP42 PSDIP42 PSDIP42 PSDIP42 PSDIP42 PSDIP42
the customer that must thoroughly check, complete, sign and return it to SGS-THOMSON. The signed list constitutes a part of the contractual agreement for the creation of the customer mask. SGS-THOMSON sales organization will provide detailed information on contractual points. Figure 34. OSD Test Character
Note: "XXX" Is the ROM code identifier that is allocated by SGS- THOMSON after receipt of all required options and the related ROM file.
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ST636x, 7x, 8x ROM MICROCONTROLLER OPTION LIST Customer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST638X SERIES Device Package Temperature Range Sales Type Marking Special Marking [ ] (d) [ ] (p) [ ] (t) [ ] (y/n) [ ] (y/n) Line 1 ".............." (N) Line 2 ".............." (N) Line 3 ".............." (N)
Traceability marking (mandatory) (d) 1 = ST6365, 2 = ST6367, 3 = ST6375, 4 = ST6377, 5 = ST6385, 6= ST6387 8 = ST6368, 9 = ST6378 (p) B = Dual in Line Plastic (t) 1 = 0 to +70 C 4 = -10 to +70 C (N) Letters, digits, `.', `-', `/' and spaces only ST638X OPTION LIST OSD Polarity Options (Put a cross on selected item) : POSITIVE NEGATIVE [] [] [] [] [] []
VSYNC, HSYNC R,G,B BLANK ST638X CHECK LIST
YES ROM CODE OSD Code: ODD & EVEN OSD Code: EEPROM Code (If Desired) [] [] [] []
NO [] [ ] For ST6365/67/75/77/85/87 [ ] For ST6368/78 []
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................................................................ Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Date . . . . . . . . . . . . . . . . . . . . .
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Notes:
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R
ST63E85,T85 ST63E87,T87
8-BIT EPROM/OTP MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING
s s s s s s s s
s
s
s
s s
s s s s s
s s
s
s
4.5 to 6V supply operating range 8MHz Maximum Clock Frequency User Program ROM: up to 20140 bytes Reserved Test ROM: up to 340 bytes Data ROM: user selectable size Data RAM: 256 bytes Data EEPROM: 384 bytes 42-Pin Shrink Dual in Line Plastic Package for OTP versions 42-Pin Shrink Dual in Line Ceramic Package for EPROM versions Up to 22 software programmable general purpose Inputs/Outputs, including 2 direct LED driving Outputs Two Timers each including an 8-bit counter with a 7-bit programmable prescaler Digital Watchdog Function Serial Peripheral Interface (SPI) supporting SBUS/ I 2 C BUS and standard serial protocols SPI for external frequency synthesis tuning 14 bit counter for voltage synthesis tuning Up to Six 6-Bit PWM D/A Converters AFC A/D converter with 0.5V resolution Five interrupt vectors (IRIN/NMI, Timer 1 & 2, VSYNC, PWR INT.) On-chip clock oscillator 5 Lines by 15 Characters On-Screen Display Generator with 128 Characters All ROM types are supported by pin-to-pin EPROM and OTP versions. The development tool of the ST6365, ST6375, ST6385, ST6367, ST6377, ST6387 microcontrollers consists of the ST638X-EMU2 emulation and development system to be connected via a standard RS232 serial line to an MS-DOS Personal Computer.
PSDIP42
CSDIP42
(Refer to end of Document for Ordering Information)
DEVICE SUMMARY
EPROM DEVICE ST63E85 ST63E87 OTP DEVICE ST63T85 ST63T87
ROM
(Bytes) 20K 20K
D/A Converter 4 6
Rev. 2.2
December 1997
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
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1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST63E8x microcontrollers are members of the 8-bit HCMOS ST638x family, a series of devices specially oriented to TV applications. Different ROM size and peripheral configurations are available to give the maximum application and cost flexibility. They are the EPROM/OTP versions of the ST636x, 7x, 8x, ROM devices and are suitable for product prototyping and low volume production. All ST638x members are based on a building block approach: a common core is surrounded by a combination of on-chip peripherals (macrocells) available from a standard library. These peripherals are designed with the same Core technology providing full compatibility and short design time. Many of these macrocells are specially dedicated to TV applications. The macrocells of the ST638x Table 1. Device Summary
Device ST63E85 ST63T85 ST63E87 ST63T87 EPROM (Bytes) 20K 20K 20K OTP (Bytes) 20K RAM (Bytes) 256 256 256 256 EEPROM (Bytes) 384 384 384 384 AFC Yes Yes Yes Yes VS Yes Yes Yes Yes D/A 4 4 6 6 Colour Pins 3 3 3 3 Target R0M Devices ST6365, 75, 85 ST6365, 75, 85 ST6367, 77 87 ST6367, 77 87
family are: two Timer peripherals each including an 8-bit counter with a 7-bit software programmable prescaler (Timer), a digital hardware activated watchdog function (DHWD), a 14-bit voltage synthesis tuning peripheral, a Serial Peripheral Interface (SPI), up to six 6-bit PWM D/A converters, an AFC A/D converter with 0.5V resolution, an onscreen display (OSD) with 15 characters per line and 128 characters (in two banks each of 64 characters). In addition the following memory resources are available: program EPROM (up to 20K), data RAM (256 bytes), EEPROM (384 bytes). Refer to pin configurations figures and to ST638x device summary (Table 1) for the definition of ST638x family members and a summary of differences among the different types.
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Figure 1. Block Diagram
PORT A TEST TEST PORT B IRIN/PC6 INTERRUPT Inputs DATA ROM USER SELECTABLE DATA RAM 256 Bytes DATA EEPROM 384 Bytes PORT C
PA0 - PA7* PB0 - PB2, PB4 PB6*
USER PROGRAM MEMORY UP TO 20KBytes
Serial Peripheral Interface
PC2, PC4 - PC7* PC0/SCL PC1/SDA PC3/SEN
TIMER 1
TIMER 2
PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER SUPPLY OSCILLATOR RESET 8 BIT CORE
Digital Watchdog Timer D/A Outputs VS Output & AFC Outputs On-Screen Display DA0 - DA5
AFC & VS* R, G, B, BLANK HSYNC, VSYNC
VDD VSS
OSCin OSCout
RESET
OSDOSCout
OSDOSCin VR01753
*Refer to Pin Description for Additional Information
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1.2 PIN DESCRIPTION VDD and VSS. Power is supplied to the MCU using these two pins. VDD is power and VSS is the ground connection. OSCin, OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the correct operation of the MCU with various stability/ cost trade-offs. The OSCin pin is the input pin, the OSCout pin is the output pin. RESET. The active low RESET pin is used to start the microcontroller to the beginning of its program. Additionally the quartz crystal oscillator will be disabled when the RESET pin is low to reduce power consumption during reset phase. TEST/VPP. The TEST pin must be held at VSS for normal operation. If this pin is connected to a +12.5V level during the reset phase, the EPROM programming mode is entered. PA0-PA7. These 8 lines are organized as one I/O port (A). Each line may be configured as either an input with or without pull-up resistor or as an output under software control of the data direction register. Pins PA4 to PA7 are configured as opendrain outputs (12V drive). On PA4-PA7 pins the input pull-up option is not available while PA6 and PA7 have additional current driving capability (25mA, VOL:1V). PA0 to PA3 pins are configured as push-pull. PB0-PB2, PB4-PB6. These 6 lines are organized as one I/O port (B). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register. PC0-PC7. These 8 lines are organized as one I/O port (C). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register. Pins PC0 to PC3 are configured as open-drain (5V drive) in output mode while PC4 to PC7 are open-drain with 12V drive and the input pull-up options does not exist on these four pins. PC0, PC1 and PC3 lines when in output mode are "ANDed" with the SPI control signals and are all open-drain. PC0 is connected to the SPI clock signal (SCL), PC1 with the SPI data signal (SDA) while PC3 is connected with SPI enable signal (SEN, used in S-BUS protocol). Pin PC4 and PC6 can also be inputs to software programmable edge sensitive latches which can generate interrupts; PC4 can be connected to Power Interrupt while PC6 can be connected to the IRIN/NMI interrupt line. DA0-DA5. These pins are the six PWM D/A outputs of the 6-bit on-chip D/A converters. These lines have open-drain outputs with 12V drive. The output repetition rate is 31.25KHz (with 8MHz clock). AFC. This is the input of the on-chip 10 levels comparator that can be used to implement the AFC function. This pin is an high impedance input able to withstand signals with a peak amplitude up to 12V. OSDOSCin, OSDOSCout. These are the On Screen Display oscillator terminals. An oscillation capacitor and coil network have to be connected to provide the right signal to the OSD. HSYNC, VSYNC. These are the horizontal and vertical synchronization pins. The active polarity of these pins to the OSD macrocell can be selected by the user as ROM mask option. If the device is specified to have negative logic inputs, then these signals are low the OSD oscillator stops. If the device is specified to have positive logic inputs, then when these signals are high the OSD oscillator stops. VSYNC is also con-nected to the VSYNC interrupt. R, G, B, BLANK. Outputs from the OSD. R, G and B are the color outputs while BLANK is the blanking output. All outputs are push-pull. The active polarity of these pins can be selected by the user as ROM mask option. VS. This is the output pin of the on-chip 14-bit voltage synthesis tuning cell (VS). The tuning signal present at this pin gives an approximate resolution of 40KHz per step over the UHF band. This line is a push-pull output with standard drive.
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Figure 2. ST63E65, T85 Pin configuration
VS DA1 DA2 DA3 DA4 PB0 PB1 PB2 AFC PB4 PB5 PB6 PA0 PA1 PA2 PA3 PA4 PA5 PA6 (HD0) PA7 (HD1) VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD PC0/SCL PC1/SDA PC2 PC3/SEN PC4/PWRIN PC5 PC6/IRIN PC7 RESET OSCout OSCin TEST/VPP (1) OSDOSCin OSDOSCout VSYNC HSYNC BLANK B G R
Figure 3. ST63E87, T87Pin configuration
DA0 DA1 DA2 DA3 DA4 DA5 PB1 PB2 AFC PB4 PB5 PB6 PA0 PA1 PA2 PA3 PA4 PA5 PA6 (HD0) PA7 (HD1) VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD PC0/SCL PC1/SDA PC2 PC3/SEN PC4/PWRIN PC5 PC6/IRIN VS RESET OSCout OSCin TEST/VPP (1) OSDOSCin OSDOSCout VSYNC HSYNC BLANK B G R
(1) This pin is also the VPP input for OTP/EPROM devices
(1) This pin is also the VPP input for OTP/EPROM devices
Table 2. Pin Summary
Pin Function DA0 to DA5 AFC VS R, G, B, BLANK HSYNC, VSYNC OSDOSCin OSDOSCout TEST /VPP OSCin OSCout RESET PA0- PA3 PA4- PA5 PA6- PA7 PB0- PB2 PB4- PB6 PC0- PC3 PC4- PC7 VDD, VSS Description Output, Open- Drain, 12V Input, High Impedance, 12V Output, Push- Pull Output, Push- Pull Input, Pull- up, Schmitt Trigger Input, High Impedance Output, Push- Pull Input, Pull- Down Input, Resistive Bias, Schmitt Trigger to Reset Logic Only Output, Push- Pull Input, Pull- up, Schmitt Trigger Input I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input, High Drive I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input I/ O, Push- Pull, Software Input Pull- up, Schmitt Trigger Input I/ O, Open- Drain, 5V, Software Input Pull- up, Schmitt Trigger Input I/ O, Open- Drain, 12V, No Input Pull- up, Schmitt Trigger Input Power Supply Pins
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1.3 EPROM/OTP DESCRIPTION The ST63E8x is the EPROM version of the ST636x, 7x, 8x ROM products. They are intended for use during the development of an application, and for pre-production and small volume production. The ST63T8x OTP have the same characteristics. They both include EPROM memory instead of the ROM memory of the ST638x, and so the program and constants of the program can be easily modified by the user with the ST63E8x EPROM programming board from SGS-THOMSON. The ROM mask options of the ST638x for OSD polarities (HSYNC, VSYNC, R, G, B, BLANK) are emulated with an EPROM OPTION BYTE. This is programmed by the EPROM programming board and its associated software. The EPROM Option Byte content will define the OSD options as follows:
7 0 0 0 1 0 Opt 2 Opt 1 0 Opt 0
1.4 POWER ON RESET This feature is not available on the ST63E8x, T8x. It is recommended to use the following application schematics: Figure 4. Reset Network VDD
Reset Pin
b7-3: Device specific bits, these reserved bits must be programmed with "00010". OPT 0: This bit defines the OSD H/Vsync polarity, if 0 the polarity will be negative if 1 the polarity will be positive. OPT 1: This bit defines the RGB polarity, if 0 the polarity will be negative if 1 the polarity will be positive. OPT 2: This bit defines the BLANK polarity, if 0 the polarity will be negative if 1 the polarity will be positive. From a user point of view (with the following exceptions) the ST63E8x,T8x products have exactly the same software and hardware features of the ROM version. An additional mode is used to configure the part for programming of the EPROM, this is set by a +12.5V voltage applied to the TEST/VPP pin. The programming of the ST63E8x,T8x is described in the User Manual of the EPROM Programming board. On the ST63E8x, all the 20140 bytes of PROGRAM memory are available for the user, as all the EPROM memory can be erased by exposure to UV light. On the ST63T8x (OTP device) a reserved area for test purposes exists, as for the ST638x ROM device. In order to avoid any discrepancy between program functionality when using the EPROM, OTP and ROM it is recommended NOT TO USE THESE RESERVED AREAS, even when using the ST63E8x. The Table 4 on page 10 is a summary of the EPROM/ROM Map and its reserved area.
This application schematics can also be used for the ROM devices. THE READER IS ASKED TO REFER TO THE DATASHEET OF THE ST636x, 7x, 8x ROMBASED DEVICE FOR FURTHER DETAILS. 1.5 EPROM ERASING The EPROM of the windowed package of the ST63E8x may be erased by exposure to Ultra Violet light. The erasure characteristic of the ST63E8x EPROM is such that erasure begins when the memory is exposed to light with wave lengths shorter than approximately 4000A. It should be noted that sunlight and some types of fluorescent lamps have wavelengths in the range 30004000A. It is thus recommended that the window of the ST63E8x package be covered by an opaque label to prevent unintentional erasure problems when testing the application in such an environment.The recommended erasure procedure of the ST63E8x EPROM is exposure to short wave ultraviolet light which has wavelength 2537A. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000mW/cm2 power rating. The ST63E8x should be placed within 2.5cm (1 inch) of the lamp tubes during erasure.
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2 ELECTRICAL CHARACTERISTICS
2.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, however it is advised to take normal precaution to avoid application of any voltage higher than maximum rated voltages. For proper operation it is recommended that VI and VO must be higher than VSS and smaller than VDD. Reliability is enhanced if unused inputs are connected to an appropriated logic voltage level (VDD or VSS). Power Considerations.The average chip-junction temperature, Tj, in Celsius can be obtained from: Tj= TA + PD x RthJA Where:TA = Ambient Temperature. RthJA = Package thermal resistance (junction-to ambient). PD = Pint + Pport. Pint = IDD x VDD (chip internal power). Pport = Port power dissipation (determined by the user).
Value -0.3 to 7.0 VSS - 0.3 to +13 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to +13 VSS - 0.3 to VDD + 0.3 - 0.3 to 13.0 + 10 + 50 50 150 150 Unit V V V V V V mA mA mA mA C
Symbol VDD VI VI VO VO VPP IO IO IVDD IVSS Tj
Parameter Supply Voltage Input Voltage (AFC IN) Input Voltage (Other inputs) Output Voltage (PA4-PA7, PC4-PC7, DA0-DA5) Output Voltage (Other outputs) EPROM Programming Voltage Current Drain per Pin Excluding VDD, VSS, PA6, PA7 Current Drain per Pin (PA6, PA7) Total Current into VDD (source) Total Current out of VSS (sink) Junction Temperature
THERMAL CHARACTERISTICS
Symbol RthJA Parameter Thermal Resistance Test Conditions PSDIP42 Min. Value Typ. Max. 67 Unit C/W
2.2 RECOMMENDED OPERATING CONDITIONS
Symbol TA VDD VPP fOSC fOSDOSC Parameter Operating Temperature Operating Supply Voltage EPROM Programming Voltage Oscillator Frequency RUN & WAIT Modes On-screen Display Oscillator Frequency Test Conditions Min. 0 4.5 12.0 Value Typ. 5.0 12.5 8.0 Max. 70 6.0 13.0 8.1 8.0 Unit C V V MHz MHz
EEPROM INFORMATION The ST63xx EEPROM single poly process has been specially developed to achieve 300.000 Write/Erase cycles and a 10 years data retention.
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2.3 DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C unless otherwise specified). Table 3: DC ELECTRICAL CHARACTERISTICS
Symbol VIL VIH VHYS Parameter Input Low Level Voltage Input High Level Voltage Hysteresis Voltage(1) Test Conditions All I/O Pins All I/O Pins All I/O Pins VDD = 5V DA0-DA5, PB0-PB6, OSD Outputs, PC0-PC7, O0, O1, PA0-PA5 VDD = 4.5V IOL= 1.6mA IOL= 5.0mA PA6-PA7 VDD = 4.5V IOL= 1.6mA IOL= 25mA OSDOSCout OSCout VDD = 4.5V IOL= 0.4mA VS Output VDD = 4.5V IOL= 0.5mA IOL= 1.6mA PB0-PB7, PA0-PA3, OSD Outputs VDD = 4.5V IOH = - 1.6mA OSDOSCout, OSCout, VDD = 4.5V IOH= - 0.4mA VS Output VDD = 4.5V IOH= - 0.5mA PB0-PB6, PA0-PA3, PC0-PC3, VIN= VSS OSCin VIN= VSS VIN= VDD OSCin All I/O Input Mode no pull-up OSDOSCin VIN= VDD or VSS Min. 0.8xVDD 1.0 Value Typ. Max. 0.2xVDD Unit V V V
VOL
Low Level Output Voltage
0.4 1.0
V V
VOL
Low Level Output Voltage
0.4 1.0 0.4
V V V
VOL
Low Level Output Voltage
VOL
Low Level Output Voltage
0.4 1.0 4.1
V V V
VOH
High Level Output Voltage
VOH
High Level Output Voltage
4.1
V
VOH
High Level Output Voltage Input Pull Up Current Input Mode with Pull-up Input Leakage Current Input Pull-down current in RESET Input Leakage Current RAM Retention Voltage in RESET Input Leakage Current
4.1
V
IPU IIL IIH IIL IIL IIH VDDRAM IIL IIH
- 100
- 50
- 25
mA
- 10 0.1 100
-1 1
- 0.1 10
A A A
-10
10
A
1.5 Reset Pin with Pull-up VIN= VSS - 50 - 30 - 10
V A
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Table 3: DC ELECTRICAL CHARACTERISTICS
Symbol IIL IIH Parameter Test Conditions AFC Pin VIH= VDD VIL= VSS VIH = 12.0V DA0-DA5, PA4-PA5, PC0-PC7, O0, O1 VOH = VDD DA0-DA5, PA4-PA7, PC4-PC7, O0, O1 VOH = 12V fOSC= 8MHz, ILoad= 0mA VDD= 6.0V fOSC= 8MHz, ILoad= 0mA VDD= 6V fOSC= Not App, ILoad= 0mA VDD= 6V RESET Pin RESET Pin A/D AFC Pin VDD= 5V A/D AFC Pin Relative to other levels VDD= 5V 0.8xVDD 200 100 Min. Value Typ. Max. 1 -1 40 10 A A mA mA mA V V mV mV Unit
Input Leakage Current
A
IOH
Output Leakage Current Output Leakage Current High Voltage Supply Current RUN Mode Supply Current WAIT Mode Supply Current at transition to RESET Reset Trigger Level ON Reset Trigger Level OFF Input Level Absolute Tolerance Input Level Relatice Tolerance(1)
IOH IDD IDD IDD VON VOFF VTA VTR
40 6 3 0.1 16 10 1 0.3xVDD
Note 1. Not 100% Tested
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2.4 AC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C, fOSC=8MHz, VDD=4.5 to 6.0V unless otherwise specified)
Symbol tWRES tOHL tOHL Parameter Minimum Pulse Width High to Low Transition Time High to Low Transition Time Test Conditions RESET Pin PA6, PA7 VDD = 5V, CL = 1000pF (2) DA0-DA5, PB0-PB6, OSD Outputs, PC0-PC7 VDD = 5V, CL = 100pF (2) PB0-PB6, PA0-PA3, OSD Outputs, PC0-PC3 VDD = 5V, CL = 100pF PB0-PB6, PA0-PA3, OSD Outputs, PC0-PC3 VDD = 5V, CL = 100pF Min. 125 Value Typ. Max. Unit ns 100 20 ns ns
tOLH
Low to High Transition Time
20
ns
Data HOLD Time SPI after clock goes low ICBUS/S-BUS only D/A Converter Repetition FrefDA quency (1) SIO Baudrate (1) fSIO tWEE EEPROM Write Time EEPROM WRITE/ERASE CyEndurance cles Retention EEPROM Data Retention (4) CIN Input Capacitance (3) COUT Output Capacitance (3) COSCin, Oscillator Pins Internal (3) COSCout Capacitance tOH COSDin, Oscillator Pins External COSDout Capacitance
175 31.25 62.50 5 >1 million
ns kHz kHz ms cycles years pF pF pF 25 pF
TA = 25C One Byte QA LOT Acceptance Criteria TA = 25C All Inputs Pins All Outputs Pins
10
300,000 10
10 10 5 15
Notes: 1. A clock other than 8MHz will affect the frequency response of those peripherals (D/A, and SPIs) whose clock is derived from the system clock. 2. The rise and fall times of PORT A have been increased in order to avoid current spikes while maintaining a high drive capability 3. Not 100% Tested 4. Based on extrapolated data
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3 GENERAL INFORMATION
3.1 ORDERING INFORMATION The following chapter deals with the procedure for transfer the Program/Data ROM codes to SGSTHOMSON. Communication of the ROM Codes. To communicate the contents of Program/Data ROM memories to SGS-THOMSON, the customer must send: - one file in INTEL INTELLEC 8/MDS FORMAT (either as an EPROM or as a MS-DOS diskette) for the PROGRAM Memory; - one file in INTEL INTELLEC 8/MDS FORMAT (either as an EPROM or as a MS-DOS diskette) for the EEPROM initial content (this file is optional). The program ROM should respect the ROM Memory Map as in Table 4. The ROM code must be generated with an ST6 assembler. Before programming the EPROM, the EPROM programmer buffer must be filled with FFh. For shipment to SGS-THOMSON, the master EPROMs should be placed in a conductive IC carrier and packed carefully. 3.2 CUSTOMER EEPROM INITIAL CONTENTS: FORMAT a. The content should be written into an INTEL INTELLEC format file. b In the case of 384 bytes of EEPROM, the starting address is 000h and the end address is 7Fh. The order of the pages (64 bytes each) is an in the specification (i.e. b7, b1 b0: 001, 010, 011, 101, 110. 111). c. Undefined or don't care bytes should have the content FFh. 3.3 OSD TEST CHARACTER IN ORDER TO ALLOW THE TESTING OF THE ON-CHIP OSD MACROCELL THE FOLLOWING CHARACTER MUST BE PROVIDED AT THE FIXED 3Fh (63) POSITION OF THE SECOND OSD BANK. Listing Generation & Verification. When SGS-THOMSON receives the files, a computer listing is generated from them. This listing refers extractly to the mask that will be used to produce the microcontroller. Then the listing is returned to the customer that must thoroughly check, complete, sign and return it to SGS-THOMSON. The signed list constitutes a part of the contractual agreement for the creation of the customer mask. SGS-THOMSON sales organization will provide detailed information on contractual points. Figure 5. OSD Test Character
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3.4 PACKAGE MECHANICAL DATA Figure 6. 42-Pin Plastic Shrink Dual-In-Line Package
Dim. A
E A2 A1 A L e b2 D b C E1 eA eB E .015 GAGE PLANE LEAD DETAIL eB
mm Min 0.51 3.05 3.81 0.46 1.02 0.23 15.24 1.78 15.24 18.54 1.52 0.000 2.54 3.30 0.25 0.56 1.14 Typ Max 5.08 0.020 Min
inches Typ Max 0.200
A1 A2 b b2 C D E E1 e eA
VR01725G eC
4.57 0.120 0.150 0.180 0.018 0.022 0.040 0.045
0.38 0.009 0.010 0.015 16.00 0.600 0.070 0.600 0.730 0.060 0.630
36.58 36.83 37.08 1.440 1.450 1.460 12.70 13.72 14.48 0.500 0.540 0.570
eB eC L N
3.56 0.100 0.130 0.140 42
Number of Pins
Figure 7. 42-Pin Ceramic Shrink Dual-In-Line Package
mm Min 0.76 Typ Max 4.01 0.030 Min inches Typ Max 0.158
Dim. A A1 B B1 C D D1 e G G2 L S CDIP42SO O N
0.38 0.46 0.56 0.015 0.018 0.022 0.76 0.89 1.02 0.030 0.035 0.040 0.23 0.25 0.38 0.009 0.010 0.015 36.68 37.34 38.00 1.444 1.470 1.496 35.56 1.78 1.400 0.070
E1 14.48 14.99 15.49 0.570 0.590 0.610 12.70 12.95 13.21 0.500 0.510 0.520 1.14 2.92 0.89 5.08 0.115 0.035 0.350 Number of Pins 42 0.045 0.200
G1 12.70 12.95 13.21 0.500 0.510 0.520
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ST63E8x, T8x MICROCONTROLLER OPTION LIST
Customer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST63T8X SERIES Device Package Temperature Range Sales Type Marking Special Marking [ ] (d) [ ] (p) [ ] (t) [ ] (y/n) [ ] (y/n) Line 1 ".............." (N) Line 2 ".............." (N) Line 3 ".............." (N)
Traceability marking (mandatory) (d) 1 = ST63T85, 2 = ST63T87, 3 = ST63T78 (p) B = Dual in Line Plastic (t) 1 = 0 to +70 C (N) Letters, digits, '.', '-', '/' and spaces only ST63T8X CHECK LIST YES OSD Code: ODD & EVEN OSD Code: [] [] NO [ ] For ST63T85/T87 [ ] For ST63T78
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................................................... ......... Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Date . . . . . . . . . . . . . . . . . . . . .
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3.5 Ordering Information Table
Sales Type ST63E85D1/ XX ST63E87D1/ XX ST63T85B1/ XX ST63T87B1/ XX EPROM/ EEPROM Size 20K/ 384 Bytes 20K/ 384 Bytes 20K/ 384 Bytes 20K/ 384 Bytes D/ A Converter 4 6 4 6 Temperature Range 0 to + 70 C 0 to + 70 C 0 to + 70 C 0 to + 70 C Package CSDIP42W CSDIP42W PSDIP42 PSDIP42
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics.
(c)1997 SGS-THOMSON Microelectronics - All Rights Reserved. Purchase of Components by SGS-THOMSON Microelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. I2 C
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